Daihan Wang - Citegraph

Author Info

Name	Affiliation	Papers
DAIHAN WANG	Keio Univ, Kohoku Ku, 3-14-1 Hiyoshi, Yokohama, Kanagawa 2238522, Japan	8
Collaborators	Citations	PageRank
5	82	4.78
Referers	Referees	References
189	155	85

Search Limit

100189

Publications (8 rows)

Collaborators (5 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Dynamic Link-Width Optimization for Network-on-Chip	0	0.34	2011
A Link Removal Methodology For Application-Specific Networks-On-Chip On Fpgas	0	0.34	2009
A Link Removal Methodology For Networks-On-Chip On Reconfigurable Systems	3	0.41	2008
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks	25	0.97	2008
Run-time power gating of on-chip routers using look-ahead routing	45	1.39	2008
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs	0	0.34	2007
A Temporal Correlation Based Port Combination Methodology For Networks-On-Chip On Reconfigurable Systems	3	0.42	2007
A Parametric Study of Scalable Interconnects on FPGAs	6	0.57	2006

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