Name
Title | Citations | PageRank | Year |
|---|---|---|---|
| Statistical delay computation considering spatial correlations | 63 | 5.53 | 2003 |
| A precorrected-FFT method for simulating on-chip inductance | 0 | 0.34 | 2002 |
| Worst case clock skew under power supply variations | 10 | 0.75 | 2002 |
| Inductance 101: analysis and design issues | 24 | 2.45 | 2001 |
| On-chip inductance modeling | 2 | 0.63 | 2000 |
| Fast analysis and optimization of power/ground networks | 49 | 3.82 | 2000 |
| On-chip inductance modeling and analysis | 39 | 3.42 | 2000 |