Chong Sang Kim - Citegraph

Author Info

Name	Affiliation	Papers
CHONG SANG KIM	SEOUL NATL UNIV, DEPT COMP ENGN, SEOUL 151742, SOUTH KOREA	22
Collaborators	Citations	PageRank
46	629	57.96
Referers	Referees	References
1032	275	203

Search Limit

1001000

Publications (22 rows)

Collaborators (46 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Adaptive routing considering the number of available wavelengths in WDM networks	4	0.52	2003
An accurate and practical buffer allocation model for the buffer cache based on marginal gains	0	0.34	2003
Practical adaptive routing schemes considering load balancing in WDM networks	0	0.34	2003
Bounding Cache-Related Preemption Delay for Real-Time Systems	49	3.31	2001
A Low-Overhead, High-Performance Unified Buffer Management Scheme That Exploits Sequential and Looping References.	0	0.34	2000
A predictive call admission control scheme for low Earth orbit satellite networks	2	0.72	2000
A low-overhead high-performance unified buffer management scheme that exploits sequential and looping references	59	2.85	2000
On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies	106	5.85	1999
Cache-Conscious Limited Preemptive Scheduling	5	0.50	1999
U-cache: A cost-effective solution to the virtual cache synonym problem	1	0.38	1998
Virtual backup network for broadband network restoration	0	0.34	1998
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling	57	3.30	1997
Cache performance improvement through on-demand, in-cache page clearing	0	0.34	1997
Efficiently supporting hard/soft deadline transactions in real-time database systems	7	0.65	1996
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling	148	6.42	1996
An accurate worst case timing analysis for RISC processors	153	23.33	1995
Worst case timing analysis of RISC processors: R3000/R3010 case study	23	4.96	1995
A worst case timing analysis technique for instruction prefetch buffers	6	0.60	1994
Competitive learning neural network with dynamic output neuron generation	0	0.34	1994
Multiple neural networks using the reduced input dimension	0	0.34	1994
Threaded prefetching: an adaptive instruction prefetch mechanism	8	1.83	1993
V-P cache: a storage efficient virtual cache organization	1	0.37	1993