| HFOS $$_L$$ L : hyper scale fast optical switch-based data center network with L-level sub-network | 0 | 0.34 | 2022 |
| Tolerating Permanent Faults With Low-Energy Overhead in Multicore Mixed-Criticality Systems | 1 | 0.35 | 2022 |
| A Survey of Fault-Tolerance Techniques for Embedded Systems From the Perspective of Power, Energy, and Thermal Issues | 0 | 0.34 | 2022 |
| TherMa-MiCs: Thermal-Aware Scheduling for Fault-Tolerant Mixed-Criticality Systems | 0 | 0.34 | 2022 |
| Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators | 0 | 0.34 | 2021 |
| Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators | 0 | 0.34 | 2020 |
| Partition Pruning: Parallelization-Aware Pruning for Deep Neural Networks. | 0 | 0.34 | 2019 |
| Low-overhead thermally resilient optical network-on-chip architecture | 1 | 0.36 | 2019 |
| PyCM: Multiclass confusion matrix library in Python. | 0 | 0.34 | 2018 |
| SPONGE: A Scalable Pivot-based On/Off Gating Engine for Reducing Static Power in NoC Routers | 1 | 0.34 | 2018 |
| DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture. | 4 | 0.43 | 2018 |
| SMART: A scalable mapping and routing technique for power-gating in NoC routers | 1 | 0.35 | 2017 |
| Heterogeneous redundancy to address performance and cost in multi-core SIMT: work-in-progress | 0 | 0.34 | 2017 |
| Thermal and power aware task mapping on 3D Network on Chip | 5 | 0.44 | 2016 |
| AdapNoC: A fast and flexible FPGA-based NoC simulator | 5 | 0.43 | 2016 |
| Impact of on-chip power distribution on Temperature-Induced Faults in Optical NoCs | 0 | 0.34 | 2016 |
| TooT: an efficient and scalable power-gating method for NoC routers | 9 | 0.47 | 2016 |
| A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard. | 2 | 0.40 | 2016 |
| Power-efficient prefetching on GPGPUs | 2 | 0.36 | 2015 |
| Application-based dynamic reconfiguration in optical network-on-chip. | 2 | 0.36 | 2015 |
| Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality | 3 | 0.39 | 2015 |
| All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip | 11 | 0.61 | 2014 |
| Towards a scalable, low-power all-optical architecture for networks-on-chip | 5 | 0.41 | 2014 |
| QuT: A low-power optical Network-on-Chip | 11 | 0.51 | 2014 |
| Temperature control in three-network on chips using task migration. | 1 | 0.37 | 2013 |
| ONC3: All-Optical NoC Based on Cube-Connected Cycles with Quasi-DOR Algorithm | 2 | 0.40 | 2012 |
| Scalable architecture for a contention-free optical network on-chip | 2 | 0.38 | 2012 |
| Throughput enhancement for repetitive internal cores in latency-insensitive systems | 0 | 0.34 | 2012 |
| Power-efficient deterministic and adaptive routing in torus networks-on-chip | 5 | 0.43 | 2012 |
| Hierarchical opto-electrical on-chip network for future multiprocessor architectures | 1 | 0.35 | 2011 |
| GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses | 0 | 0.34 | 2011 |
| An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC | 4 | 0.45 | 2011 |
| Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures | 2 | 0.37 | 2011 |
| All-optical wavelength-routed noc based on a novel hierarchical topology | 26 | 1.03 | 2011 |
| Efficient periodic clock calculus in latency-insensitive design | 1 | 0.37 | 2011 |
| A Low Cost circuit level fault detection technique to Full Adder design. | 2 | 0.37 | 2011 |
| Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability | 1 | 0.37 | 2010 |
| Low Power Encoding in NoCs Based on Coupling Transition Avoidance | 3 | 0.39 | 2009 |
| Contention-free on-chip routing of optical packets | 14 | 0.82 | 2009 |
| System-Level Assertion-Based Performance Verification for Embedded Systems | 0 | 0.34 | 2008 |
| Integration of System-Level IP Cores in Object-Oriented Design Methodologies | 0 | 0.34 | 2008 |
| Polymorphism-Aware Common Bus in an Object-Oriented ASIP | 0 | 0.34 | 2008 |
| An Adaptive Approach to Manage the Number of Virtual Channels | 1 | 0.36 | 2008 |
| High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs | 8 | 0.60 | 2008 |
| A Framework for Object-Oriented Embedded System Development Based on OO-ASIPs | 1 | 0.36 | 2008 |
| A Novel Partitioned Encoding Scheme for Reducing Total Power Consumption of Parallel Bus | 0 | 0.34 | 2008 |
| Energy analysis of re-injection based deadlock recovery routing algorithms | 0 | 0.34 | 2008 |
| The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model | 1 | 0.36 | 2008 |
| An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits | 1 | 0.35 | 2007 |
| Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs | 0 | 0.34 | 2007 |
