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JU-YUEH LEE
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Name
Affiliation
Papers
JU-YUEH LEE
Electrical Engineering Department, University of California, Los Angeles, CA, USA
12
Collaborators
Citations
PageRank
31
64
6.28
Referers
Referees
References
135
243
140
Search Limit
100
243
Publications (12 rows)
Collaborators (31 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
In-place LUT polarity inVersion to mitigate soft errors for FPGAs
0
0.34
2016
Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs
8
0.62
2012
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
5
0.43
2012
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults.
5
0.61
2011
Mitigating FPGA interconnect soft errors by in-place LUT inversion
7
0.55
2011
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms
7
0.59
2011
Fault modeling and characteristics of SRAM-based FPGAs (abstract only)
1
0.35
2011
RALF: reliability analysis for logic faults: an exact algorithm and its applications
4
0.48
2010
In-place decomposition for robustness in FPGA
13
0.71
2010
Fault-tolerant resynthesis with dual-output LUTs
11
0.79
2010
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction
1
0.39
2009
Low Power Scheduling Method Using Multiple Supply Voltages
2
0.41
2006
1