| Horn-ICE learning for synthesizing invariants and contracts | 5 | 0.41 | 2018 |
| Detecting All High-Level Dataraces In An Rtos Kernel | 0 | 0.34 | 2017 |
| Special issue on the 16th International Conference on Verification, Model Checking, and Abstract Interpretation. | 0 | 0.34 | 2017 |
| An Optimization Approach for Matching Textual Domain Models with Existing Code | 0 | 0.34 | 2016 |
| Model-checking trace-based information flow properties for infinite-state systems. | 0 | 0.34 | 2016 |
| Refinement-Based Verification of the FreeRTOS Scheduler in VCC. | 1 | 0.38 | 2015 |
| Verification, Model Checking, and Abstract Interpretation - 16th International Conference, VMCAI 2015, Mumbai, India, January 12-14, 2015. Proceedings | 0 | 0.34 | 2014 |
| Model-Checking Bisimulation-Based Information Flow Properties for Infinite State Systems. | 0 | 0.34 | 2012 |
| Scalable flow-sensitive pointer analysis for java with strong updates | 14 | 0.58 | 2012 |
| A compositional hierarchical monitoring automaton construction for LTL | 0 | 0.34 | 2012 |
| Model-checking trace-based information flow properties | 8 | 0.49 | 2011 |
| Dataflow analysis for datarace-free programs | 5 | 0.47 | 2011 |
| Conflict-tolerant specifications in temporal logic | 2 | 0.42 | 2010 |
| WOMM: a weak operational memory model | 0 | 0.34 | 2010 |
| Analysing Message Sequence Graph Specications | 3 | 0.44 | 2010 |
| A case study in matching service descriptions to implementations in an existing system | 2 | 0.39 | 2010 |
| Supervisory control for real-time systems based on conflict-tolerant controllers | 1 | 0.38 | 2009 |
| Conflict-Tolerant Real-Time Features | 2 | 0.43 | 2008 |
| Java memory model aware software validation | 8 | 0.54 | 2008 |
| On the Decidability of Model-Checking Information Flow Properties | 6 | 0.47 | 2008 |
| A Decidable Temporal Logic of Repeating Values | 10 | 0.69 | 2007 |
| Counter-free input-determined timed automata | 3 | 0.37 | 2007 |
| Computing Complete Test Graphs for Hierarchical Systems | 0 | 0.34 | 2006 |
| On continuous timed automata with input-determined guards | 4 | 0.41 | 2006 |
| An Automata Based Approach for Verifying Information Flow Properties | 8 | 0.52 | 2005 |
| Fault diagnosis using timed automata | 29 | 1.31 | 2005 |
| On timed automata with input-determined guards | 20 | 1.13 | 2004 |
| A Logical Characterisation of Event Clock Automata | 17 | 0.90 | 2003 |
| Timed Control Synthesis for External Specifications | 38 | 1.73 | 2002 |
| An automata-theoretic approach to constraint LTL | 37 | 1.24 | 2002 |
| A Logical Characterisation of Event Recording Automata | 5 | 0.47 | 2000 |
| Product Interval Automata: A Subclass of Timed Automata | 11 | 0.69 | 1999 |
