Marc Stöttinger - Citegraph

Author Info

Name	Affiliation	Papers
MARC STÖTTINGER	Technische Universität Darmstadt, Germany, Integrated Circuits and Systems Lab, Department of Computer Science, Technische Universität Darmstadt, Germany	20
Collaborators	Citations	PageRank
41	106	9.89
Referers	Referees	References
247	342	212

Search Limit

100342

Publications (20 rows)

Collaborators (41 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Serialized lightweight SHA-3 FPGA implementations	0	0.34	2019
Efficient Side-Channel Protections of ARX Ciphers.	0	0.34	2018
There ain't no plain key: A PUF based first-order side-channel resistant encryption construction	0	0.34	2016
Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest.	9	0.51	2014
A signature based architecture for Trojan detection	4	0.46	2014
AMASIVE: An Adaptable and Modular Autonomous Side-Channel Vulnerability Evaluation Framework.	2	0.40	2013
Among Slow Dwarfs And Fast Giants: A Systematic Design Space Exploration Of Keccak	6	0.63	2013
On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective.	0	0.34	2013
TROJANUS: An ultra-lightweight side-channel leakage generator for FPGAs	2	0.37	2013
Hardware trojan design and detection: a practical evaluation	9	0.66	2013
A new difference method for side-channel analysis with high-dimensional leakage models	9	0.91	2012
Revealing side-channel issues of complex circuits by enhanced leakage models	13	0.66	2012
Butterfly-Attack on skein's modular addition	3	0.41	2012
An adaptable, modular, and autonomous side-channel vulnerability evaluator.	2	0.39	2012
A simple power analysis attack on a McEliece cryptoprocessor	9	0.45	2011
How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power Analysis	5	0.54	2011
Secure virtualization within a multi-processor soft-core system-on-chip architecture	5	0.48	2011
Virtualization within a parallel array of homogeneous processing units	1	0.39	2010
A stochastic method for security evaluation of cryptographic FPGA implementations.	11	0.62	2010
A timing attack against patterson algorithm in the McEliece PKC	16	0.66	2009