Bodhisatwa Sadhu - Citegraph

Author Info

Name	Affiliation	Papers
BODHISATWA SADHU	IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA	26
Collaborators	Citations	PageRank
73	99	15.09
Referers	Referees	References
455	399	108

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100455

Publications (26 rows)

Collaborators (73 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams.	0	0.34	2022
Session 14 Overview - mm-Wave Transceivers for Communication and Radar Wireless Subcommittee.	0	0.34	2021
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage	0	0.34	2020
A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation.	0	0.34	2018
A 128-element Dual-Polarized Software-Defined Phased Array Radio for mm-wave 5G Experimentation.	1	0.34	2018
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions	0	0.34	2018
Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules	0	0.34	2018
Antenna-in-package design and module integration for millimeter-wave communication and 5G	0	0.34	2018
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications.	25	1.55	2017
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication	12	1.67	2017
Introduction to the Special Section on the 2016 IEEE BCTM and IEEE CSICS.	0	0.34	2017
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs	0	0.34	2016
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme	0	0.34	2015
W-band scalable phased arrays for imaging and communications	5	0.66	2015
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance	4	0.41	2015
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits.	4	0.43	2014
Building an on-chip spectrum sensor for cognitive radios.	4	0.45	2014
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits	5	0.49	2014
Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays	8	0.70	2013
Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS	11	1.08	2013
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing	3	0.52	2013
An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS	1	0.48	2012
An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS	1	0.36	2012
Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%)	0	0.34	2010
A Cmos 3.3-8.4 Ghz Wide Tuning Range, Low Phase Noise Lc Vco	14	1.86	2009
Modeling and synthesis of wide-band switched-resonators for VCOs	1	0.38	2008