Hirokatsu Shirahama - Citegraph

Author Info

Name	Affiliation	Papers
HIROKATSU SHIRAHAMA	Tohoku Univ, Res Inst Elect Commun, Sendai, Miyagi 9808577, Japan	11
Collaborators	Citations	PageRank
11	28	5.25
Referers	Referees	References
42	138	88

Search Limit

100138

Publications (11 rows)

Collaborators (11 rows)

Referers (42 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Design Of An Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link For An Asynchronous Network-On-Chip	1	0.37	2014
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link	2	0.39	2014
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link	0	0.34	2014
High-Throughput Partially Parallel Inter-Chip Link Architecture For Asynchronous Multi-Chip Nocs	0	0.34	2014
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using A Completion-Detection Scheme	2	0.50	2010
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System	2	0.44	2009
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing	4	0.50	2008
Design And Evaluation Of A 54 X 54-Bit Multiplier Based On Differential-Pair Circuitry	4	0.51	2007
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor	7	0.74	2007
Design Of A Low-Power Quaternary Flip-Flop Based On Dynamic Differential Logic	3	0.54	2006
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits	3	0.58	2006

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