Author Info
Name
Affiliation
Papers
ISHITA VERMA
Jaypee Univ Informat Technol, Dept Elect & Commun Engn, Solan 173215, HP, India
1
Collaborators
Citations 
PageRank 
4
1
0.36
Referers 
Referees 
References 
1
21
5
Title
Citations
PageRank
Year
Design and Implementation of a 64-bit RISC Processor Using VHDL10.362009