Grace Zgheib - Citegraph

Author Info

Name	Affiliation	Papers
GRACE ZGHEIB	Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland	17
Collaborators	Citations	PageRank
42	21	6.40
Referers	Referees	References
61	139	64

Search Limit

100139

Publications (17 rows)

Collaborators (42 rows)

Referers (61 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming	0	0.34	2021
Architectural Enhancements in Intel® Agilex™ FPGAs.	0	0.34	2020
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths	0	0.34	2020
Straight to the Point - Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing.	0	0.34	2020
Finding a Needle in the Haystack of Hardened Interconnect Patterns	0	0.34	2019
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.	0	0.34	2017
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.	2	0.41	2017
Automatic wire modeling to explore novel FPGA architectures	0	0.34	2016
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures.	3	0.41	2016
An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components	1	0.37	2015
A technology mapper for depth-constrained FPGA logic cells	1	0.38	2015
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations.	1	0.39	2015
Improved carry chain mapping for the VTR flow	1	0.37	2015
Revisiting and-inverter cones	8	0.55	2014
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)	3	0.43	2013
Shadow And-Inverter Cones	1	0.38	2013
Reducing the pressure on routing resources of FPGAs with generic logic chains	0	0.34	2011

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