| Stratix™ 10 High Performance Routable Clock Networks. | 3 | 0.76 | 2016 |
| Hardware Acceleration of Short Read Mapping | 53 | 2.55 | 2012 |
| Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array. | 3 | 0.50 | 2012 |
| Crunching large graphs with commodity processors | 9 | 0.58 | 2011 |
| Energy-efficient specialization of functional units in a coarse-grained reconfigurable array | 2 | 0.39 | 2011 |
| Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays | 2 | 0.41 | 2010 |
| SPR: an architecture-adaptive CGRA mapping tool | 31 | 1.25 | 2009 |
| Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays | 9 | 0.56 | 2009 |
| Abstract Verilog: A Hardware Description Language for Novice Students. | 1 | 0.43 | 2007 |
| A Type Architecture for Hybrid Micro-Parallel Computers | 3 | 0.53 | 2006 |
| Configurable Computing Platforms - Promises, Promises | 0 | 0.34 | 2006 |
| PipeRoute: a pipelining-aware router for reconfigurable architectures | 3 | 0.45 | 2006 |
| Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only) | 10 | 0.81 | 2005 |
| Architecture-Adaptive Routability-Driven Placement for FPGAs | 21 | 1.59 | 2005 |
| A compiled accelerator for biological cell signaling simulations | 18 | 1.61 | 2004 |
| Quickroute: A Fast Routing Algorithm For Pipelined Architectures | 6 | 0.61 | 2004 |
| Exploration of pipelined FPGA interconnect structures | 11 | 0.68 | 2004 |
| PipeRoute: a pipelining-aware router for FPGAs | 13 | 0.88 | 2003 |
| An Emulator for Exploring RaPiD Configurable Computing Architectures | 10 | 1.30 | 2001 |
| Distributed-memory parallel routing for field-programmable gatearrays | 10 | 0.74 | 2000 |
| Architecture Design of Reconfigurable Pipelined Datapaths | 65 | 4.60 | 1999 |
| Using precomputation in architecture and logic resynthesis | 6 | 0.63 | 1998 |
| Specifying and Compiling Applications for RaPiD | 51 | 5.56 | 1998 |
| Mapping applications to the RaPiD configurable architecture | 52 | 5.53 | 1997 |
| Configurable computing: the catalyst for high-performance architectures | 20 | 3.12 | 1997 |
| Whither configurable computing? | 0 | 0.34 | 1997 |
| Seeking Solutions in Configurable Computing | 78 | 11.04 | 1997 |
| ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing | 2 | 0.40 | 1997 |
| RaPiD - Reconfigurable Pipelined Datapath | 142 | 16.14 | 1996 |
| Architectural retiming: pipelining latency-constrained circuits | 31 | 2.20 | 1996 |
| The triptych FPGA architecture | 31 | 10.76 | 1995 |
| Placement and routing tools for the Triptych FPGA | 77 | 10.62 | 1995 |
| PathFinder: a negotiation-based performance-driven router for FPGAs | 356 | 22.62 | 1995 |
| Mesh routing topologies for multi-FPGA systems | 20 | 2.19 | 1994 |
| CRANIUM: An Interface for Message Passing on Adaptive Packet Routing Networks | 11 | 2.96 | 1994 |
| Optimal retiming of level-clocked circuits using symmetric clock schedules | 18 | 1.03 | 1994 |
| An FPGA for Implementing Asynchronous Circuits | 53 | 4.71 | 1994 |
| The practical application of retiming to the design of high-performance systems | 22 | 1.90 | 1993 |
| SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm | 56 | 4.34 | 1993 |
| The chaos router chip: design and implementation of an adaptive router | 11 | 18.83 | 1993 |
| MONTAGNE: An FPL for Synchronous and Asynchronous Circuits | 16 | 5.63 | 1992 |
| Measuring the performance potential of chess programs | 21 | 4.66 | 1990 |
| Apex: two architectures for generating parametric curves and surfaces | 5 | 1.33 | 1989 |
| WireLisp: combining graphics and procedures in a circuit specification language | 5 | 0.70 | 1989 |
| Pattern knowledge and search: the SUPREM architecture | 17 | 12.14 | 1989 |
| GeminiII: a second generation layout validation program | 9 | 1.53 | 1988 |
| The SUPREM architecture: A new intelligent paradigm | 8 | 8.31 | 1986 |
| The design and implementation of a VLSI chess move generator | 4 | 4.53 | 1984 |
