A systematic literature review on hardware implementation of artificial intelligence algorithms | 3 | 0.44 | 2021 |
System-Level Sub-20 Nm Planar And Finfet Cmos Delay Modelling For Supply And Threshold Voltage Scaling Under Process Variation | 0 | 0.34 | 2019 |
Hardware Optimized FPGA Implementations of High-Speed True Random Bit Generators Based on Switching-Type Chaotic Oscillators | 2 | 0.39 | 2019 |
Energy Optimization For Large-Scale 3d Manycores In The Dark-Silicon Era | 0 | 0.34 | 2019 |
Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms | 2 | 0.42 | 2013 |
MorphoSys reconfigurable hardware for cryptography: the twofish case | 4 | 0.45 | 2012 |
RTL delay macro-modeling with Vt and Vdd variability. | 0 | 0.34 | 2011 |
Instruction-Based Voltage Scaling For Power Reduction In Simd Mpsocs | 0 | 0.34 | 2011 |
Voltage island design in multi-core SIMD processors. | 0 | 0.34 | 2010 |
PVT variation impact on voltage island formation in MPSoC design | 6 | 0.46 | 2009 |
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms | 1 | 0.36 | 2009 |
Instruction-Set Extension for Cryptographic Applications on Reconfigurable Platform | 1 | 0.37 | 2007 |
2D and 3D Computer Graphics Algorithms under MORPHOSYS | 1 | 0.37 | 2002 |