Author Info
Name
Papers
Collaborators
H. MORINAKA
2
9
Citations 
PageRank 
Referers 
38
5.36
100
Referees 
References 
1
1
Title
Citations
PageRank
Year
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]41.101997
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture344.261996