| Hyperheuristics for explicit resource partitioning in simultaneous multithreadedprocessors | 0 | 0.34 | 2020 |
| Last level cache partitioning via multiverse thread classification | 0 | 0.34 | 2018 |
| Application of Machine Learning Techniques on Prediction of Future Processor Performance | 0 | 0.34 | 2018 |
| Dynamic Capping of Physical Register Files in Simultaneous Multi-threading Processors for Performance. | 0 | 0.34 | 2018 |
| A Machine Learning Approach For A Scalable, Energy-Efficient Utility-Based Cache Partitioning | 0 | 0.34 | 2015 |
| History-Based Predictive Instruction Window Weighting for SMT Processors | 0 | 0.34 | 2014 |
| FireSenseTB: a wireless sensor networks testbed for forest fire detection | 11 | 1.18 | 2009 |
| Dynamic resizing of superscalar datapath components for energy efficiency | 16 | 0.81 | 2006 |
| Reducing energy dissipation of wireless sensor processors using silent-store-filtering motecache | 4 | 0.48 | 2006 |
| Power efficient comparators for long arguments in superscalar processors | 2 | 0.38 | 2003 |
| Distributed Reorder Buffer Schemes for Low Power | 4 | 0.42 | 2003 |
| Energy-efficient issue queue design | 25 | 0.87 | 2003 |
| Reducing Datapath Energy through the Isolation of Short-Lived Operands | 15 | 0.71 | 2003 |
| Reducing reorder buffer complexity through selective operand caching | 63 | 3.49 | 2003 |
| Energy-Efficient Design of the Reorder Buffer | 7 | 0.54 | 2002 |
| Low-complexity reorder buffer architecture | 15 | 1.07 | 2002 |
| Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources | 94 | 4.92 | 2001 |
| Energy: efficient instruction dispatch buffer design for superscalar processors | 20 | 1.85 | 2001 |
| MaROS: A Framework for Application Development on Mobile Hosts | 0 | 0.34 | 1997 |
