Xifan Tang - Citegraph

Author Info

Name	Affiliation	Papers
XIFAN TANG	Ecole Polytech Fed Lausanne, LSI, CH-1015 Lausanne, Switzerland	32
Collaborators	Citations	PageRank
40	59	12.89
Referers	Referees	References
200	417	170

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100417

Publications (32 rows)

Collaborators (40 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs	0	0.34	2021
Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis	0	0.34	2021
Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project	0	0.34	2021
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs	0	0.34	2020
A RRAM-based FPGA for Energy-efficient Edge Computing	0	0.34	2020
A Scalable Mixed Synthesis Framework for Heterogeneous Networks.	0	0.34	2020
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs	2	0.39	2019
A Study on Switch Block Patterns for Tileable FPGA Routing Architectures	0	0.34	2019
Accelerating Inference on Binary Neural Networks with Digital RRAM Processing.	0	0.34	2019
LSOracle - a Logic Synthesis Framework Driven by Artificial Intelligence - Invited Paper.	1	0.35	2019
OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs	1	0.34	2019
Post-P&R Performance and Power Analysis for RRAM-Based FPGAs.	1	0.37	2018
Physical Design Considerations of One-level RRAM-based Routing Multiplexers.	0	0.34	2017
Optimization opportunities in RRAM-based FPGA architectures	0	0.34	2017
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.	0	0.34	2017
A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers.	1	0.35	2017
Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure.	1	0.35	2017
A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only).	0	0.34	2016
A Study on the Programming Structures for RRAM-Based FPGA Architectures.	12	0.72	2016
Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA	3	0.48	2015
Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)	0	0.34	2015
FPGA-SPICE: A simulation-based power estimation framework for FPGAs	1	0.36	2015
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells	6	0.61	2015
A study on buffer distribution for RRAM-based FPGA routing structures	1	0.37	2015
A ultra-low-power FPGA based on monolithically integrated RRAMs	2	0.44	2015
Novel configurable logic block architecture exploiting controllable-polarity transistors	0	0.34	2014
Pattern-based FPGA logic block and clustering algorithm	0	0.34	2014
A high-performance low-power near-Vt RRAM-based FPGA	4	0.47	2014
TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs	4	0.48	2014
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs	10	0.85	2014
An Enhanced Design Methodology For Resonant Clock Trees	0	0.34	2013
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise	9	0.53	2013