| Chaperone - Runtime System for Instrumenting Applications via Partial Binary Translation. | 0 | 0.34 | 2018 |
| A study of manycore shared memory architecture as a way to build SOC applications. | 0 | 0.34 | 2015 |
| Parallelization hints via code skeletonization | 0 | 0.34 | 2014 |
| 1K manycore FPGA shared memory architecture for SOC (abstract only) | 0 | 0.34 | 2014 |
| Refactoring techniques for aggressive object inlining in Java applications | 1 | 0.36 | 2012 |
| Fast Evaluation of Boolean Circuits Based on Two-Players Game and Optical Connectivity Circuits | 1 | 0.36 | 2012 |
| Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, Haifa, Israel, May 24-26, 2010 | 22 | 1.78 | 2010 |
| HparC: a mixed nested shared memory and message passing programming style intended for grid | 0 | 0.34 | 2010 |
| Code alignment for architectures with pipeline group dispatching | 0 | 0.34 | 2010 |
| Aggressive function inlining: preventing loop blockings in the instruction cache | 1 | 0.36 | 2008 |
| Complementing missing and inaccurate profiling using a minimum cost circulation algorithm | 7 | 0.67 | 2008 |
| Overlapping memory operations with circuit evaluation in reconfigurable computing | 2 | 0.38 | 2006 |
| Reducing program image size by extracting frozen code and data | 2 | 0.37 | 2004 |
| Efficient parallel solutions of linear algebraic circuits | 3 | 0.42 | 2004 |
| Optimization opportunities created by global data reordering | 9 | 1.12 | 2003 |
| Parallel Solutions of Simple Indexed Recurrence Equations | 3 | 0.42 | 2001 |
| Parallel Solutions of Indexed Recurrence Equations | 2 | 0.42 | 1997 |
| On the usage of simulators to detect inefficiency of parallel programs caused by “bad” schedulings: the SIMPARC approach | 2 | 0.49 | 1996 |
