| Hybrid Eye-Tracking on a Smartphone with CNN Feature Extraction and an Infrared 3D Model. | 1 | 0.35 | 2020 |
| Automatic Topology Optimization for FPGA Interconnect Synthesis | 0 | 0.34 | 2018 |
| Smarteye: An Accurate Infrared Eye Tracking System For Smartphones | 1 | 0.37 | 2018 |
| High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. | 2 | 0.39 | 2018 |
| Energy efficient object detection on the mobile GP-GPU | 1 | 0.34 | 2017 |
| High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors | 4 | 0.51 | 2016 |
| Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. | 3 | 0.44 | 2016 |
| Performance characterization of mobile GP-GPUs | 0 | 0.34 | 2015 |
| Automatic FPGA system and interconnect construction with multicast and customizable topology | 3 | 0.52 | 2015 |
| Fine-Grained Interconnect Synthesis | 4 | 0.44 | 2015 |
| Towards interconnect-adaptive packing for FPGAs | 9 | 0.57 | 2014 |
| VTR 7.0: Next Generation Architecture and CAD System for FPGAs | 124 | 4.04 | 2014 |
| Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design | 3 | 0.46 | 2014 |
| Efficient methods for out-of-order load/store execution for high-performance soft processors | 1 | 0.38 | 2013 |
| The VTR project: architecture and CAD for FPGAs from verilog to routing | 138 | 6.38 | 2012 |
| Portable, flexible, and scalable soft vector processors | 12 | 0.69 | 2012 |
| On the difficulty of pin-to-wire routing in FPGAs. | 3 | 0.47 | 2012 |
| An Energy-Efficient, Fast Fpga Hardware Architecture For Opencv-Compatible Object Detection | 6 | 0.57 | 2012 |
| A new, fast algorithm for detecting protein coevolution using maximum compatible cliques. | 1 | 0.38 | 2011 |
| Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect | 27 | 1.49 | 2011 |
| Comparing FPGA vs. custom cmos and the impact on processor microarchitecture | 55 | 2.90 | 2011 |
| The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop | 0 | 0.34 | 2011 |
| Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design | 10 | 0.71 | 2011 |
| FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy | 13 | 1.86 | 2009 |
| Soft vector processors vs FPGA custom hardware: measuring and reducing the gap | 0 | 0.34 | 2009 |
| VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling | 70 | 3.41 | 2009 |
| Fine-grain performance scaling of soft vector processors | 10 | 0.80 | 2009 |
| The evolution of architecture exploration of programmable devices | 0 | 0.34 | 2009 |
| Data parallel FPGA workloads: Software versus hardware | 6 | 0.58 | 2009 |
| Modeling routing demand for early-stage FPGA architecture development | 22 | 1.05 | 2008 |
| Automated transistor sizing for FPGA architecture exploration | 14 | 1.35 | 2008 |
| VESPA: portable, scalable, and flexible FPGA-based vector processors | 51 | 2.95 | 2008 |
| Portable and scalable FPGA-based acceleration of a direct linear system solver | 13 | 1.10 | 2008 |
| Architecting Hard Crossbars On Fpgas And Increasing Their Area Efficiency With Shadow Clusters | 5 | 0.62 | 2007 |
| Exploration and Customization of FPGA-Based Soft Processors | 10 | 0.83 | 2007 |
| Measuring the Gap Between FPGAs and ASICs | 424 | 21.39 | 2007 |
| FPGA Architecture: Survey and Challenges | 50 | 1.95 | 2007 |
| Application-specific customization of soft processor microarchitecture | 39 | 3.08 | 2006 |
| Invited Keynote 1: Closing the gap between FPGAs and ASICs. | 1 | 0.40 | 2006 |
| Reconfigurable hardware implementation of a phase-correlation stereoalgorithm | 27 | 0.95 | 2006 |
| Using Bus-Based Connections To Improve Field-Programmable Gate-Array Density For Implementing Datapath Circuits | 18 | 1.11 | 2006 |
| Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters | 20 | 1.22 | 2006 |
| A Verilog RTL Synthesis Tool for Heterogeneous FPGAs | 12 | 1.48 | 2005 |
| The Stratix II logic and routing architecture | 100 | 8.71 | 2005 |
| The Transmogrifier-4: an FPGA-based hardware development system with multi-gigabyte memory capacity and high host and memory bandwidth | 5 | 0.87 | 2005 |
| The microarchitecture of FPGA-based soft processors | 42 | 3.22 | 2005 |
| Design, layout and verification of an FPGA using automated tools | 21 | 2.37 | 2005 |
| Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs | 0 | 0.34 | 2004 |
| A synthesis oriented omniscient manual editor | 0 | 0.34 | 2004 |
| Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits | 7 | 0.50 | 2004 |
