| Collaborative Adaptation for Energy-Efficient Heterogeneous Mobile SoCs | 1 | 0.37 | 2020 |
| Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores | 3 | 0.40 | 2019 |
| Momentum: Power-neutral Performance Scaling with Intrinsic MPPT for Energy Harvesting Computing Systems. | 2 | 0.39 | 2019 |
| BRB: Mitigating Branch Predictor Side-Channels. | 7 | 0.47 | 2019 |
| Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE | 2 | 0.38 | 2019 |
| Runtime Performance and Power Optimization of Parallel Disparity Estimation on Many-Core Platforms. | 0 | 0.34 | 2018 |
| High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation. | 2 | 0.36 | 2018 |
| Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations. | 1 | 0.35 | 2018 |
| Hardware-Validated CPU Performance and Energy Modelling | 1 | 0.36 | 2018 |
| Online Concurrent Workload Classification For Multi-Core Energy Management | 0 | 0.34 | 2018 |
| Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs. | 5 | 0.45 | 2017 |
| Machine learning for run-time energy optimisation in many-core systems. | 0 | 0.34 | 2017 |
| Nucleus: Finding the Sharing Limit of Heterogeneous Cores. | 1 | 0.36 | 2017 |
| Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs. | 14 | 0.75 | 2017 |
| Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture | 16 | 0.94 | 2011 |
| Defect-tolerant N2-transistor structure for reliable nanoelectronic designs | 4 | 0.48 | 2009 |
| Design of a low power MPEG-1 motion vector reconstructor | 0 | 0.34 | 2009 |
| Enhancing Delay Fault Coverage Through Low-Power Segmented Scan | 21 | 0.77 | 2007 |
| Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection | 4 | 0.45 | 2007 |
| Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities | 22 | 1.08 | 2005 |
| Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction | 123 | 4.17 | 2004 |
| Power profile manipulation: a new approach for reducing test application time under power constraints | 16 | 0.81 | 2002 |
| Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs | 1 | 0.36 | 1999 |
