| 3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS | 8 | 0.86 | 2015 |
| A 0.5–16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS | 10 | 1.00 | 2015 |
| 2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS | 11 | 1.01 | 2014 |
| Session 10 overview: Analog techniques. | 0 | 0.34 | 2013 |
| F6: Mixed-signal/RF design and modeling in next-generation CMOS. | 0 | 0.34 | 2013 |
| A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs | 4 | 0.62 | 2013 |
| Design of high-speed wireline transceivers for backplane communications in 28nm CMOS | 10 | 1.14 | 2012 |
| A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS | 15 | 2.60 | 2012 |
| Session 21 overview: Analog techniques: Analog subcommittee. | 0 | 0.34 | 2012 |
| Technologies that could change the world - You decide! | 1 | 0.40 | 2012 |
| High-speed transceivers: Standards, challenges, and future. | 0 | 0.34 | 2011 |
| Time-Variant Characterization And Compensation Of Wideband Circuits | 1 | 0.44 | 2007 |
| A new technique for characterization of digital-to-analog converters in high-speed systems | 3 | 0.58 | 2007 |
| Will continued process-node shrinks kill high-performance analog design? | 0 | 0.34 | 2005 |
| Clocking circuits for wireline communications | 0 | 0.34 | 2005 |
| Design of half-rate clock and data recovery circuits for optical communication systems | 4 | 0.60 | 2001 |
| A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector | 87 | 16.55 | 2001 |
