Andrea Bonfanti - Citegraph

Author Info

Name	Affiliation	Papers
ANDREA BONFANTI	Department of Electronics, Information and Bioengineering, Politecnico di Milano, Milan, Italy	29
Collaborators	Citations	PageRank
66	269	36.37
Referers	Referees	References
662	387	181

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100662

Publications (29 rows)

Collaborators (66 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations	0	0.34	2022
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters	0	0.34	2022
A Generalization of the Groszkowski’s Result in Differential Oscillator Topologies	1	0.36	2021
Fully Integrated, 406 <inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>A, <inline-formula><tex-math notation="LaTeX">$\text{5 }^{\circ}$</tex-math></inline-formula>/hr, Full Digital Output Lissajous Frequency-Modulated Gyroscope	0	0.34	2019
Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops.	0	0.34	2018
High Scale-Factor Stability Frequency-Modulated MEMS Gyroscope: 3-Axis Sensor and Integrated Electronics Design.	0	0.34	2018
An Efficient Tool for the Assisted Design of SAR ADCs Capacitive DACs	1	0.39	2016
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS.	0	0.34	2016
A 64-Channel 965- $\mu\text{W}$ Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS	0	0.34	2016
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters	1	0.35	2015
A tool for the assisted design of charge redistribution SAR ADCs.	2	0.39	2015
Analysis and optimization of a SAR ADC with attenuation capacitor	1	0.36	2014
A Modeling Environment for the Simulation and Design of Charge Redistribution DACs Used in SAR ADCs	0	0.34	2014
A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs	1	0.40	2014
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band	7	0.73	2013
Efficient Calculation of the Impulse Sensitivity Function in Oscillators.	5	0.51	2012
Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators	14	0.84	2012
A fast and accurate simulation method of impulse sensitivity function in oscillators.	0	0.34	2012
A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission	12	1.38	2010
A low-power integrated circuit for analog spike detection and sorting in neural prosthesis systems	1	0.40	2009
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35- $\mu$ m CMOS	7	0.69	2008
5-Ghz Oscillator Array With Reduced Flicker Up-Conversion In 0.13-Mu M Cmos	13	1.36	2006
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs.	9	0.76	2006
Phase Noise And Accuracy In Quadrature Oscillators	24	2.64	2004
Differential tuning oscillators with reduced flicker noise upconversion.	0	0.34	2004
A multi-tank LC-oscillator [microwave oscillator example]	0	0.34	2004
A Dds-Based Pll For 2.4-Ghz Frequency Synthesis	4	0.65	2003
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion	76	9.89	2002
Analysis and design of a 1.8-GHz CMOS LC quadrature VCO	90	10.56	2002