Hee-Chul Yun - Citegraph

Author Info

Name	Affiliation	Papers
HEE-CHUL YUN	Korea Adv Inst Sci & Technol, Comp Architecture Lab, Yusong Gu, Taejon 305701, South Korea	31
Collaborators	Citations	PageRank
47	321	18.81
Referers	Referees	References
743	827	407

Search Limit

100827

Publications (31 rows)

Collaborators (47 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Virtual Gang Scheduling of Parallel Real-Time Tasks	1	0.35	2021
An Analyzable Inter-core Communication Framework for High-Performance Multicore Embedded Systems	0	0.34	2021
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors	1	0.35	2020
Exploiting DRAM bank mapping and HugePages for effective denial-of-service attacks on shared cache in multicore.	1	0.36	2020
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms	0	0.34	2020
SpectreGuard: An Efficient Data-centric Defense Mechanism against Spectre Attacks	5	0.43	2019
Denial-of-Service Attacks on Shared Cache in Multicore: Analysis and Prevention	4	0.42	2019
RT-Gang: Real-Time Gang Scheduling Framework for Safety-Critical Systems	2	0.38	2019
DeepPicar: A Low-Cost Deep Neural Network-Based Autonomous Car	6	0.55	2018
Protecting Real-Time GPU Kernels on Integrated CPU-GPU SoC Platforms.	0	0.34	2018
BWLOCK: A Dynamic Memory Access Control Framework for Soft Real-Time Applications on Multicore Platforms.	7	0.54	2017
Protecting Real-Time GPU Applications on Integrated CPU-GPU SoC Platforms.	2	0.40	2017
Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems.	0	0.34	2017
Addressing isolation challenges of non-blocking caches for multicore real-time systems.	2	0.38	2017
Real-Time Computing on Multicore Processors.	7	0.45	2016
Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems	7	0.52	2016
Global Real-Time Memory-Centric Scheduling for Multicore Systems.	13	0.72	2016
A Simplex Architecture for Intelligent and Safe Unmanned Aerial Vehicles	4	0.45	2016
WCET(m) Estimation in Multi-core Systems Using Single Core Equivalence	18	0.64	2015
MEDUSA: A Predictable and High-Performance DRAM Controller for Multicore Based Embedded Systems	8	0.44	2015
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms	76	1.87	2014
S3A: secure system simplex architecture for enhanced security and robustness of cyber-physical systems	25	0.88	2013
MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms	5	0.43	2013
Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality	61	1.77	2012
S3A: Secure System Simplex Architecture for Enhanced Security of Cyber-Physical Systems	10	0.84	2012
Deterministic Real-time Thread Scheduling	0	0.34	2011
A reduced complexity design pattern for distributed hierarchical command and control system	3	0.42	2010
A framework for the safe interoperability of medical devices in the presence of network failures	28	1.78	2010
System-Wide Energy Optimization for Multiple DVS Components and Real-Time Tasks	5	0.46	2010
An Efficient Lock Protocol for Home-Based Lazy Release Consistency	13	0.74	2001
Adaptive prefetching technique for shared virtual memory	7	0.56	2001