| A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations | 0 | 0.34 | 2022 |
| A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters | 0 | 0.34 | 2022 |
| A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler | 1 | 0.35 | 2022 |
| A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter | 2 | 0.36 | 2022 |
| A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping | 1 | 0.35 | 2022 |
| Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise | 0 | 0.34 | 2022 |
| A 12.9-To-15.1ghz Digital Pll Based On A Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter | 0 | 0.34 | 2021 |
| A 98.4fs-Jitter 12.9-To-15.1ghz Pll-Based Lo Phase-Shifting System With Digital Background Phase-Offset Correction For Integrated Phased Arrays | 0 | 0.34 | 2021 |
| A Novel Topology of Coupled Phase-Locked Loops | 1 | 0.39 | 2021 |
| A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs | 6 | 0.46 | 2021 |
| Jitter Minimization in Digital PLLs with Mid-Rise TDCs | 3 | 0.38 | 2020 |
| A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-<italic>N</italic> Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking | 1 | 0.35 | 2020 |
| A 66fs(Rms) Jitter 12.8-To-15.2ghz Fractional-N Bang-Bang Pll With Digital Frequency-Error Recovery For Fast Locking | 0 | 0.34 | 2020 |
| 17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. | 0 | 0.34 | 2020 |
| A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. | 0 | 0.34 | 2019 |
| A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS | 4 | 0.40 | 2019 |
| A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. | 7 | 0.46 | 2019 |
| Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper) | 0 | 0.34 | 2019 |
| Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops | 3 | 0.39 | 2019 |
| PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. | 5 | 0.46 | 2018 |
| A Background Calibration Technique to Control the Bandwidth of Digital PLLs. | 1 | 0.35 | 2018 |
| A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. | 5 | 0.55 | 2018 |
| Analysis Of Millimeter-Wave Digital Frequency Modulators For Ubiquitous Sensors And Radars | 0 | 0.34 | 2017 |
| A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL | 0 | 0.34 | 2017 |
| A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop | 15 | 0.81 | 2015 |
| An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs | 28 | 1.32 | 2014 |
| Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops | 16 | 0.95 | 2014 |
| 21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC | 10 | 1.08 | 2014 |
| Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs | 8 | 0.70 | 2013 |
| A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. | 0 | 0.34 | 2013 |
| Nonlinearity cancellation in digital PLLs (Invited paper) | 0 | 0.34 | 2013 |
| An efficient method to compute phase-noise in injection-locked frequency dividers | 0 | 0.34 | 2013 |
| Minimum-jitter design of bang-bang PLLs in the presence of 1/f2 and 1/f3 DCO noise | 0 | 0.34 | 2013 |
| Background adaptive linearization of high-speed digital-to-analog Converters | 0 | 0.34 | 2013 |
| Efficient Calculation of the Impulse Sensitivity Function in Oscillators. | 5 | 0.51 | 2012 |
| A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. | 7 | 0.51 | 2012 |
| A 20Mb/s phase modulator based on a 3.6GHz digital PLL with −36dB EVM at 5mW power | 3 | 0.49 | 2012 |
| A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation | 34 | 2.10 | 2011 |
| Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs | 7 | 0.58 | 2011 |
| A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- Integrated Jitter at 4.5-mW Power | 15 | 0.71 | 2011 |
| Low-Power Divider Retiming in a | 1 | 0.35 | 2011 |
| Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. | 2 | 0.36 | 2011 |
| Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. | 1 | 0.38 | 2010 |
| AD-PLL for WiMAX with digitally-regulated TDC and glitch correction logic | 0 | 0.34 | 2010 |
| A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. | 14 | 2.21 | 2010 |
| Time-to-digital converter with 3-ps resolution and digital linearization algorithm | 9 | 1.09 | 2010 |
| Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL | 20 | 1.60 | 2010 |
| Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division | 5 | 0.53 | 2010 |
| A glitch-corrector circuit for low-spur ADPLLs | 4 | 0.73 | 2009 |
| Noise analysis and minimization in bang-bang digital PLLs | 37 | 2.24 | 2009 |
