José A. Tierno - Citegraph

Author Info

Name	Affiliation	Papers
JOSÉ A. TIERNO	IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA	16
Collaborators	Citations	PageRank
65	206	26.21
Referers	Referees	References
734	323	67

Search Limit

100734

Publications (16 rows)

Collaborators (65 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology	7	1.19	2015
A 28 GHz Hybrid PLL in 32 nm SOI CMOS	9	1.02	2014
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits	5	0.49	2014
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI	5	0.71	2013
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing	3	0.52	2013
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation	38	2.33	2012
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS	28	3.02	2012
An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS	1	0.48	2012
A 45nm Cmos Neuromorphic Chip With A Scalable Architecture For Learning In Networks Of Spiking Neurons	19	1.18	2011
Indirect phase noise sensing for self-healing voltage controlled oscillators.	4	0.81	2011
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.	17	2.42	2009
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS	3	0.52	2008
A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI.	2	0.47	2008
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI.	9	2.06	2007
Integrated transversal equalizers in high-speed fiber-optic systems	40	6.94	2003
A 100-MIPS GaAs Asynchronous Microprocessor	16	2.05	1994

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