| Reconfigurable Switched-Capacitor Dc-Dc Converter With Adaptive Switch Modulation And Frequency Scaling Techniques | 0 | 0.34 | 2021 |
| A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration | 0 | 0.34 | 2020 |
| A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. | 0 | 0.34 | 2019 |
| A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique | 0 | 0.34 | 2019 |
| A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System | 0 | 0.34 | 2018 |
| An 89.55dB-SFDR 179.6dB-FoM<inf>s</inf> 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration | 0 | 0.34 | 2018 |
| A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting. | 0 | 0.34 | 2018 |
| A Current Average Control Method For Transient-Glitch Reduction In Variable Frequency Dc-Dc Converters | 0 | 0.34 | 2017 |
| A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. | 0 | 0.34 | 2016 |
| A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC | 0 | 0.34 | 2016 |
| An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. | 2 | 0.38 | 2016 |
| A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique | 0 | 0.34 | 2016 |
| A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration | 4 | 0.47 | 2014 |
| 11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS | 44 | 3.37 | 2014 |
| A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS | 6 | 0.50 | 2014 |
| A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC. | 5 | 0.56 | 2013 |
| A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time. | 0 | 0.34 | 2012 |
| A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS | 9 | 2.92 | 2012 |
| A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC | 8 | 0.58 | 2012 |
| A High-Efficiency CMOS DC-DC Converter With 9- $\ \mu$ s Transient Recovery Time | 6 | 0.61 | 2012 |
| A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop | 0 | 0.34 | 2010 |
| A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13- $\mu$ m CMOS | 1 | 0.38 | 2009 |
| A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-<formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>m CMOS | 7 | 0.91 | 2009 |
| A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming | 1 | 0.39 | 2006 |
| A 14-b 20-Msamples/s CMOS pipelined ADC | 0 | 0.34 | 2001 |
| Characterization Of 1/F Noise Vs. Number Of Gate Stripes In Mos Transistors | 0 | 0.34 | 1999 |
