Vasilios Kelefouras - Citegraph

Author Info

Name	Affiliation	Papers
VASILIOS KELEFOURAS	University of Patras, Patras, Greece	14
Collaborators	Citations	PageRank
13	27	5.28
Referers	Referees	References
67	713	428

Search Limit

100713

Publications (14 rows)

Collaborators (13 rows)

Referers (67 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A methodology correlating code optimizations with data memory accesses, execution time and energy consumption	1	0.48	2019
A methodology for efficient code optimizations and memory management	1	0.40	2018
Workflow Simulation Aware and Multi-threading Effective Task Scheduling for Heterogeneous Computing.	0	0.34	2018
Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management.	1	0.36	2018
Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management	1	0.36	2017
A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details.	2	0.35	2017
A high-performance matrix–matrix multiplication methodology for CPU and GPU architectures	3	0.38	2016
A methodology for speeding up loop kernels by exploiting the software information and the memory architecture	1	0.35	2015
A Matrix–Matrix Multiplication methodology for single/multi-core architectures using SIMD	7	0.46	2014
A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization	3	0.39	2014
A scalable and near-optimal representation of access schemes for memory management	1	0.35	2014
A systematic approach to classify design-time global scheduling techniques	4	0.39	2013
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints	0	0.34	2013
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes	2	0.36	2013

1