Wulong Liu - Citegraph

Author Info

Name	Affiliation	Papers
WULONG LIU	Tsinghua Univ, Dept EE, TNList, Beijing 100084, Peoples R China	24
Collaborators	Citations	PageRank
92	12	8.36
Referers	Referees	References
41	311	86

Search Limit

100311

Publications (24 rows)

Collaborators (92 rows)

Referers (41 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Generalizable Floorplanner through Corner Block List Representation and Hypergraph Embedding	0	0.34	2022
LHNN: lattice hypergraph neural network for VLSI congestion prediction	0	0.34	2022
What about Inputting Policy in Value Function: Policy Representation and Policy-Extended Value Function Approximator.	0	0.34	2022
Lb-Despot: Efficient Online Pomdp Planning Considering Lower Bound In Action Selection (Student Abstract)	0	0.34	2021
Relational Navigation Learning in Continuous Action Space among Crowds	0	0.34	2021
Adaptive Online Packing-guided Search for POMDPs.	0	0.34	2021
Enhancing Context-Based Meta-Reinforcement Learning Algorithms Via An Efficient Task Encoder (Student Abstract)	0	0.34	2021
Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction	0	0.34	2021
Foresee Then Evaluate: Decomposing Value Estimation With Latent Future Prediction	0	0.34	2021
Towards Effective Context For Meta-Reinforcement Learning: An Approach Based On Contrastive Learning	0	0.34	2021
Reinforcement Learning based Negotiation-aware Motion Planning of Autonomous Vehicles	0	0.34	2021
Addressing Action Oscillations Through Learning Policy Inertia	0	0.34	2021
An Efficient Transfer Learning Framework for Multiagent Reinforcement Learning.	0	0.34	2021
Efficient Deep Reinforcement Learning via Adaptive Policy Transfer	0	0.34	2020
Multi-Agent Interactions Modeling with Correlated Policies	1	0.35	2020
Triple-GAIL: A Multi-Modal Imitation Learning Framework with Generative Adversarial Nets	1	0.35	2020
Neighborhood Cognition Consistent Multi-Agent Reinforcement Learning	0	0.34	2020
MGHRL - Meta Goal-Generation for Hierarchical Reinforcement Learning.	0	0.34	2020
Modeling and optimization of low power resonant clock mesh	0	0.34	2015
Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis	0	0.34	2015
Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case	3	0.45	2014
Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects	1	0.35	2014
TSV-aware topology generation for 3D Clock Tree Synthesis	5	0.44	2013
On-chip hybrid power supply system for wireless sensor nodes	1	0.34	2011