Name
Title | Citations | PageRank | Year |
|---|---|---|---|
| A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications | 2 | 0.51 | 2012 |
| Macro-modeling concepts for the chip electrical interface | 0 | 0.34 | 2002 |
| Dynamic Receiver Biasing For Inter-Chip Communication | 0 | 0.34 | 2001 |
| CGaAs PowerPC FXU | 1 | 0.44 | 2000 |
| Overview of complementary GaAs technology for high-speed VLSI circuits | 2 | 0.60 | 1998 |