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TAKESHI FUJINO
Author Info
Open Visualization
Name
Affiliation
Papers
TAKESHI FUJINO
Ritsumeikan Univ, Dept VLSI Syst Design, Shiga, Japan
25
Collaborators
Citations
PageRank
52
16
8.98
Referers
Referees
References
70
159
69
Search Limit
100
159
Publications (25 rows)
Collaborators (52 rows)
Referers (70 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Practical Aspects on Non-profiled Deep-learning Side-channel Attacks against AES Software Implementation with Two Types of Masking Countermeasures including RSM
0
0.34
2021
Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface
1
0.38
2021
Towards Trained Model Confidentiality And Integrity Using Trusted Execution Environments
0
0.34
2021
Model Reverse-Engineering Attack Against Systolic-Array-Based Dnn Accelerator Using Correlation Power Analysis
0
0.34
2021
Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks
1
0.35
2020
Exploring Effect of Residual Electric Charges on Cryptographic Circuits
0
0.34
2020
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator
0
0.34
2020
Cause Analysis Method of Entropy Loss in Physically Unclonable Functions
0
0.34
2020
Deep Learning Side-Channel Attack Against Hardware Implementations of AES
0
0.34
2019
Tamper-Resistant Authentication System With Side-Channel Attack Resistant Aes And Puf Using Mdr-Rom
1
0.34
2015
Reversing stealthy dopant-level circuits
7
0.52
2015
Diffusion Programmable Device : The device to prevent reverse engineering.
0
0.34
2014
Unified Coprocessor Architecture For Secure Key Storage And Challenge-Response Authentication
1
0.37
2014
Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA
0
0.34
2014
Security Evaluation Of Rg-Dtm Puf Using Machine Learning Attacks
0
0.34
2014
Development Of Compression Tolerable And Highly Implementable Watermarking Method For Mobile Devices
1
0.35
2014
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)
1
0.36
2013
Via Programmable Structured Asic Architecture "Vpex3" And Cad Design System
0
0.34
2012
High Uniqueness Arbiter-Based Puf Circuit Utilizing Rg-Dtm Scheme For Identification And Authentication Applications
3
0.56
2012
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit
0
0.34
2012
Improved Via-Programmable Structured Asic Vpex3 And Its Evaluation
0
0.34
2012
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL
0
0.34
2011
Placement Tool Dedicated for a Via-Programmable Logic Device VPEX.
0
0.34
2010
Architecture Of Via Programmable Logic Using Exclusive-Or Array (Vpex) For Eb Direct Writing
0
0.34
2007
A Low Power Embedded Dram Macro For Battery-Operated Lsis
0
0.34
2003
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