Baher Haroun - Citegraph

Author Info

Name	Affiliation	Papers
BAHER HAROUN	Texas Instruments Inc, Dallas, TX 75243 USA	18
Collaborators	Citations	PageRank
56	34	9.20
Referers	Referees	References
153	273	89

Search Limit

100273

Publications (18 rows)

Collaborators (56 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation	0	0.34	2022
A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing	0	0.34	2022
Autonomous Vehicles Sensor Needs.	0	0.34	2018
A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS.	0	0.34	2017
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners	7	0.64	2015
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications	0	0.34	2015
A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS	0	0.34	2014
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS.	8	1.06	2014
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops.	3	0.47	2013
Session 16 overview: Switching power control techniques: Analog subcommittee	0	0.34	2012
Low power ADC's for wireless communications	0	0.34	2012
A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS.	15	2.26	2012
A sigma-delta ADC with decimation and gain control function for a Bluetooth receiver in 130 nm digital CMOS	0	0.34	2006
Synthesis of signal processing structured datapaths for FPGAs supporting RAMs and busses	0	0.34	1995
Floorplanning with datapath optimization	0	0.34	1995
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs	0	0.34	1994
A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic	0	0.34	1994
A floorplanner driven by structural and timing constraints	1	0.36	1994

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