| Layout Capacitance Extraction Using Automatic Pre-Characterization and Machine Learning | 0 | 0.34 | 2020 |
| Fast Electromagnetic Transient Simulation Based on Hierarchical Low-Rank Approximation | 0 | 0.34 | 2019 |
| Capacitance Extraction With Provably Good Absorbing Boundary Conditions. | 0 | 0.34 | 2018 |
| Research on the DFT of ZC Sequence in TD-LTE System. | 0 | 0.34 | 2016 |
| Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit | 2 | 0.38 | 2016 |
| Macro Model of Advanced Devices for Parasitic Extraction. | 0 | 0.34 | 2016 |
| Low-Complexity Carrier Frequency Offset Estimation Algorithm in TD-LTE. | 2 | 0.54 | 2013 |
| $O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks | 3 | 0.41 | 2012 |
| Lagrangian relaxation for gate implementation selection | 3 | 0.40 | 2011 |
| Numerical simulation of viscous flow over non-smooth surfaces | 0 | 0.34 | 2011 |
| Ultra-fast interconnect driven cell cloning for minimizing critical path delay | 2 | 0.39 | 2010 |
| Fast characterization of parameterized cell library | 1 | 0.43 | 2009 |
| The impact of BEOL lithography effects on the SRAM cell performance and yield | 6 | 0.54 | 2009 |
| Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials | 0 | 0.34 | 2009 |
| SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes | 1 | 0.37 | 2008 |
| A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics | 6 | 0.55 | 2008 |
| Circuit-wise buffer insertion and gate sizing algorithm with scalability | 3 | 0.45 | 2008 |
| Multi-scenario buffer insertion in multi-core processor designs | 2 | 0.39 | 2008 |
| Buffering Interconnect for Multicore Processor Designs | 1 | 0.45 | 2008 |
| Wire Sizing for Non-Tree Topology | 10 | 0.69 | 2007 |
| Fast capacitance extraction in multilayer, conformal and embedded dielectric using hybrid boundary element method | 2 | 0.44 | 2007 |
| An O(bn2) time algorithm for optimal buffer insertion with b buffer types | 9 | 0.63 | 2007 |
| A new twisted differential line structure in global bus design | 2 | 0.37 | 2007 |
| Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method | 5 | 0.49 | 2007 |
| An Efficient Algorithm for RLC Buffer Insertion | 0 | 0.34 | 2007 |
| A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects | 7 | 0.79 | 2007 |
| Probabilistic Congestion Prediction with Partial Blockages | 5 | 0.52 | 2007 |
| Path-Based Buffer Insertion | 1 | 0.41 | 2007 |
| An O(Bn(2)) Time Algorithm For Optimal Buffer Insertion With B Buffer Types | 12 | 0.79 | 2006 |
| A New RLC Buffer Insertion Algorithm | 3 | 0.41 | 2006 |
| Model order reduction of linear networks with massive ports via frequency-dependent port packing | 15 | 0.79 | 2006 |
| An O(mn) time algorithm for optimal buffer insertion of nets with m sinks | 9 | 0.77 | 2006 |
| Fast algorithms for slew constrained minimum cost buffering | 44 | 2.02 | 2006 |
| An Efficient, Scalable Hardware Engine for Boolean SATisfiability | 2 | 0.39 | 2006 |
| Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction | 1 | 0.38 | 2006 |
| A fast algorithm for optimal buffer insertion | 24 | 1.18 | 2005 |
| Sparse transformations and preconditioners for 3-D capacitance extraction | 5 | 0.66 | 2005 |
| A vector-based approach for power supply noise analysis in test compaction. | 19 | 1.06 | 2005 |
| Static Compaction of Delay Tests Considering Power Supply Noise | 9 | 0.55 | 2005 |
| The rectilinear Steiner arborescence problem is NP-complete | 27 | 1.48 | 2005 |
| Path based buffer insertion | 20 | 1.29 | 2005 |
| Making fast buffer insertion even faster via approximation techniques | 16 | 0.89 | 2005 |
| K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits | 72 | 3.05 | 2004 |
| A statistical fault coverage metric for realistic path delay faults | 14 | 0.89 | 2004 |
| A divide-and-conquer algorithm for 3-D capacitance extraction | 3 | 0.52 | 2004 |
| A Divide-and-Conquer Algorithm for 3D Capacitance Extraction | 2 | 0.43 | 2004 |
| Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics | 4 | 0.63 | 2004 |
| A circuit level fault model for resistive shorts of MOS gate oxide | 4 | 0.57 | 2004 |
| Minimum moment Steiner trees | 2 | 0.45 | 2004 |
| PARADE: PARAmetric Delay Evaluation under Process Variation | 4 | 0.47 | 2004 |
