| Counteract Side-Channel Analysis of Neural Networks by Shuffling | 0 | 0.34 | 2022 |
| ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses<sup/> | 0 | 0.34 | 2022 |
| Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs | 0 | 0.34 | 2022 |
| Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. | 0 | 0.34 | 2022 |
| TOFU - Toggle Count Analysis made simple. | 0 | 0.34 | 2022 |
| Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM | 0 | 0.34 | 2022 |
| A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. | 0 | 0.34 | 2022 |
| On the application of Two-Photon Absorption for Laser Fault Injection attacks Pushing the physical boundaries for Laser-based Fault Injection. | 0 | 0.34 | 2022 |
| Hardware Accelerated FrodoKEM on RISC-V | 0 | 0.34 | 2022 |
| Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC | 0 | 0.34 | 2022 |
| Post-Quantum Signatures on RISC-V with Hardware Acceleration. | 0 | 0.34 | 2022 |
| Domrep-An Orthogonal Countermeasure For Arbitrary Order Side-Channel And Fault Attack Protection | 0 | 0.34 | 2021 |
| Finding The Needle In The Haystack: Metrics For Best Trace Selection In Unsupervised Side-Channel Attacks On Blinded Rsa | 0 | 0.34 | 2021 |
| Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability | 0 | 0.34 | 2021 |
| The Cost of OSCORE and EDHOC for Constrained Devices | 0 | 0.34 | 2021 |
| Algebraic Fault Analysis of Subterranean 2.0 | 0 | 0.34 | 2021 |
| Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks | 0 | 0.34 | 2021 |
| Machine learning and structural characteristics for reverse engineering. | 2 | 0.38 | 2020 |
| Secure and User-Friendly Over-the-Air Firmware Distribution in a Portable Faraday Cage | 0 | 0.34 | 2020 |
| TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing | 0 | 0.34 | 2020 |
| Review of error correction for PUFs and evaluation on state-of-the-art FPGAs | 1 | 0.36 | 2020 |
| Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks | 0 | 0.34 | 2020 |
| Efficient hardware/software co-design for post-quantum crypto algorithm SIKE on ARM and RISC-V based microcontrollers | 2 | 0.37 | 2020 |
| A Power Side-Channel Attack on the CCA2-Secure HQC KEM | 0 | 0.34 | 2020 |
| Timing Resilience for Efficient and Secure Circuits. | 0 | 0.34 | 2020 |
| Logic Locking Induced Fault Attacks | 0 | 0.34 | 2020 |
| RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. | 0 | 0.34 | 2020 |
| Secure Physical Enclosures from Covers with Tamper-Resistance. | 0 | 0.34 | 2019 |
| EyeSec - A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. | 0 | 0.34 | 2019 |
| Improving on State Register Identification in Sequential Hardware Reverse Engineering | 0 | 0.34 | 2019 |
| Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC | 0 | 0.34 | 2019 |
| A Calibratable Detector for Invasive Attacks | 3 | 0.45 | 2019 |
| Machine learning and structural characteristics for reverse engineering. | 0 | 0.34 | 2019 |
| Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists | 0 | 0.34 | 2019 |
| Experimental Power and Performance Evaluation of CAESAR Hardware Finalists | 0 | 0.34 | 2018 |
| High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And An Improved Construction. | 0 | 0.34 | 2018 |
| Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors | 0 | 0.34 | 2018 |
| Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. | 0 | 0.34 | 2018 |
| The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. | 6 | 0.50 | 2018 |
| The CAESAR-API in the real world — Towards a fair evaluation of hardware CAESAR candidates | 1 | 0.48 | 2018 |
| 18 Seconds to Key Exchange: Limitations of Supersingular Isogeny Diffie-Hellman on Embedded Devices. | 0 | 0.34 | 2018 |
| Dividing the threshold: Multi-probe localized EM analysis on threshold implementations | 2 | 0.39 | 2018 |
| Fast and Reliable PUF Response Evaluation from Unsettled Bistable Rings | 0 | 0.34 | 2017 |
| ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications. | 0 | 0.34 | 2017 |
| A security-aware routing implementation for dynamic data protection in zone-based MPSoC. | 2 | 0.38 | 2017 |
| How To Break Secure Boot On Fpga Socs Through Malicious Hardware | 3 | 0.40 | 2017 |
| Compromising FPGA SoCs using malicious hardware blocks. | 1 | 0.39 | 2017 |
| Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. | 4 | 0.45 | 2017 |
| Towards post-quantum security for IoT endpoints with NTRU. | 2 | 0.42 | 2017 |
| Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs. | 5 | 0.44 | 2017 |
