| Page Size Aware Cache Prefetching | 0 | 0.34 | 2022 |
| SIMD-Matcher: A SIMD-based Arbitrary Matching Framework | 0 | 0.34 | 2022 |
| Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems | 1 | 0.35 | 2022 |
| Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing | 0 | 0.34 | 2022 |
| OpenMem: Hardware/Software Cooperative Management for Mobile Memory System | 0 | 0.34 | 2021 |
| Automatic Microprocessor Performance Bug Detection | 1 | 0.35 | 2021 |
| SEEC: stochastic escape express channel | 0 | 0.34 | 2021 |
| An FPGA-based Hybrid Memory Emulation System | 0 | 0.34 | 2021 |
| Pitstop: Enabling a Virtual Network Free Network-on-Chip | 1 | 0.35 | 2021 |
| KVRAID - high performance, write efficient, update friendly erasure coding scheme for KV-SSDs. | 0 | 0.34 | 2021 |
| Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs | 1 | 0.35 | 2020 |
| A Generic FPGA Accelerator for Minimum Storage Regenerating Codes | 0 | 0.34 | 2020 |
| Hardware Memory Management for Future Mobile Hybrid Memory Systems | 1 | 0.35 | 2020 |
| Virtualize and share non-volatile memories in user space | 0 | 0.34 | 2020 |
| DRAIN: Deadlock Removal for Arbitrary Irregular Networks | 3 | 0.43 | 2020 |
| SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors | 0 | 0.34 | 2020 |
| The Best of IEEE Computer Architecture Letters in 2018 | 0 | 0.34 | 2019 |
| vNVML: An Efficient User Space Library for Virtualizing and Sharing Non-Volatile Memories | 0 | 0.34 | 2019 |
| SpecLock: Speculative Lock Forwarding | 0 | 0.34 | 2019 |
| GenMatcher: A Generic Clustering-Based Arbitrary Matching Framework. | 0 | 0.34 | 2019 |
| Optimizing Post-Copy Live Migration with System-Level Checkpoint Using Fabric-Attached Memory | 1 | 0.35 | 2019 |
| SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution | 3 | 0.42 | 2019 |
| Perceptron-based prefetch filtering | 8 | 0.48 | 2019 |
| Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom. | 1 | 0.35 | 2018 |
| MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. | 2 | 0.36 | 2018 |
| Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. | 7 | 0.43 | 2017 |
| Speculative paging for future NVM storage. | 2 | 0.38 | 2017 |
| Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. | 1 | 0.36 | 2016 |
| Path confidence based lookahead prefetching. | 10 | 0.46 | 2016 |
| Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects | 1 | 0.34 | 2015 |
| Shared Last-Level Caches and The Case for Longer Timeslices | 1 | 0.36 | 2015 |
| Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors | 1 | 0.35 | 2015 |
| A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms | 12 | 0.66 | 2015 |
| Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management | 2 | 0.36 | 2015 |
| Wear-Aware Adaptive Routing for Networks-on-Chips | 0 | 0.34 | 2015 |
| Bandwidth-efficient on-chip interconnect designs for GPGPUs | 28 | 0.88 | 2015 |
| Dynamic Memory Pressure Aware Ballooning | 3 | 0.39 | 2015 |
| LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip | 16 | 0.69 | 2014 |
| Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip | 3 | 0.40 | 2014 |
| Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management | 17 | 0.62 | 2014 |
| Power gating with block migration in chip-multiprocessor last-level caches | 9 | 0.48 | 2013 |
| Bidirectional interconnect design for low latency high bandwidth NoC | 2 | 0.39 | 2013 |
| GCA: Global congestion awareness for load balance in Networks-on-Chip. | 16 | 0.67 | 2013 |
| Dynamic voltage and frequency scaling for shared resources in multicore processor designs | 24 | 0.79 | 2013 |
| ARI: Adaptive LLC-memory traffic management | 9 | 0.49 | 2013 |
| Use it or lose it: wear-out and lifetime in future chip multiprocessors | 21 | 0.81 | 2013 |
| LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures | 9 | 0.53 | 2012 |
| In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches | 15 | 0.64 | 2012 |
| Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router | 1 | 0.35 | 2012 |
| B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors | 5 | 0.44 | 2012 |
