A Digitally-Controlled Smps Using A Novel High-Resolution Dpwm Generator Based On A Pseudo Relaxation-Oscillation Technique | 0 | 0.34 | 2013 |
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture | 3 | 0.50 | 2012 |
A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. | 1 | 0.36 | 2011 |
Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches | 1 | 0.36 | 2008 |
A Novel High-Speed And Low-Voltage Cmos Level-Up/Down Shifter Design For Multiple-Power And Multiple-Clock Domain Chips | 2 | 0.39 | 2007 |
Fast And Accurate Power Bus Designer For Multi-Layers High-Speed Digital Boards | 0 | 0.34 | 2006 |
Proxy caching scheme based on the characteristics of streaming media contents on the internet | 0 | 0.34 | 2004 |