| New Concept for Fault Current Limiter With Voltage Restoration Capability | 0 | 0.34 | 2020 |
| Mitigation of Positive Zero Effect on Nonminimum Phase Boost DC-DC Converters in CCM. | 2 | 0.46 | 2018 |
| Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach. | 1 | 0.36 | 2017 |
| A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution. | 2 | 0.40 | 2016 |
| A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation. | 0 | 0.34 | 2016 |
| Envelope tracking using transient waveform switching shaping supply modulation | 4 | 0.41 | 2015 |
| Complex QR Decomposition Using Fast Plane Rotations for MIMO Applications | 4 | 0.46 | 2014 |
| Estimation of passive mixer output bandwidth using switched-capacitor techniques. | 0 | 0.34 | 2013 |
| Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management | 2 | 0.47 | 2012 |
| Alien crosstalk mitigation in vectored DSL systems for backhaul applications | 3 | 0.49 | 2012 |
| A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. | 10 | 0.99 | 2011 |
| Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop | 1 | 0.38 | 2011 |
| A generic scalable architecture for min-sum/offset-min-sum unit for irregular/regular LDPC decoder | 3 | 0.50 | 2010 |
| Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding | 4 | 0.43 | 2010 |
| Design of a link-controller architecture for multiple serial link protocols. | 0 | 0.34 | 2010 |
| A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers | 19 | 1.59 | 2009 |
| Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation | 0 | 0.34 | 2009 |
| Iterative(Turbo) Iq Imbalance Estimation And Correction In Bicm-Id For Flat Fading Channels | 4 | 0.47 | 2007 |
| Effect of Word-length Precision on the Performance of MIMO Systems | 0 | 0.34 | 2007 |
| Time-Domain Modeling Of A Phase-Domain All-Digital Phase-Locked Loop For Rf Applications | 3 | 0.47 | 2007 |
| Exploring Logic Block Granularity in Leakage Tolerant FPGA | 0 | 0.34 | 2006 |
| Generalized Signal Reconstruction Method For Designing Interpolation Filters | 1 | 0.38 | 2006 |
| A nonredundant ternary CAM circuit for network search engines | 7 | 0.64 | 2006 |
| Generic Network Interfaces for Plug and Play NoC Based Architecture | 0 | 0.34 | 2006 |
| A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter | 22 | 4.01 | 2006 |
| SoC with an integrated DSP and a 2.4-GHz RF transmitter | 4 | 0.84 | 2005 |
| The impact of inductance on transients affecting gate oxide reliability | 0 | 0.34 | 2005 |
| FPGA Architecture for Standby Power Management | 7 | 0.63 | 2005 |
| Exploiting temporal idleness to reduce leakage power in programmable architectures | 18 | 1.11 | 2005 |
| Power switch network design for MTCMOS | 6 | 0.56 | 2005 |
| Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA | 3 | 0.52 | 2005 |
| Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines | 12 | 0.76 | 2005 |
| VHDL Simulation and Modeling of an All-Digital RF Transmitter | 4 | 0.80 | 2005 |
| All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS | 108 | 19.85 | 2004 |
| PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks | 10 | 0.82 | 2004 |
| Interconnect Modeling for Copper/Low-k Technologies | 1 | 0.37 | 2004 |
| Event-Driven Simulation And Modeling Of An Rf Oscillator | 3 | 2.78 | 2004 |
| Benchmarks for Interconnect Parasitic Resistance and Capacitance | 11 | 2.00 | 2003 |
| Challenges in integrated CMOS transceivers for short distance wireless | 0 | 0.34 | 2001 |
| Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels | 5 | 0.80 | 2001 |
| High-performance energy-efficient D-flip-flop circuits | 22 | 2.28 | 2000 |
| Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels | 0 | 0.34 | 2000 |
| Energy optimization of multilevel cache architectures for RISC and CISC processors | 31 | 6.75 | 1998 |
| Leap frog multiplier | 1 | 0.48 | 1996 |
| Design techniques for high-performance, energy-efficient control logic | 5 | 5.12 | 1996 |
| Leap frog multiplier | 2 | 0.54 | 1996 |
| Short-circuit power driven gate sizing technique for reducing power dissipation | 10 | 5.72 | 1995 |
| Energy optimization of multi-level processor cache architectures | 18 | 12.12 | 1995 |
| Low-power design techniques for high-performance CMOS adders | 29 | 7.18 | 1995 |
| Intermediate-level vision tasks on a memory array architecture. | 5 | 0.59 | 1992 |
