| Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC) | 0 | 0.34 | 2015 |
| Electrical characterization of integrated passive devices using thin film technology for 3D integration | 0 | 0.34 | 2013 |
| Electrical characterization of integrated passive devices using thin film technology for 3D integration | 0 | 0.34 | 2013 |
| Research on deep RIE-based through-si-via micromachining for 3-D system-in-package integration | 0 | 0.34 | 2009 |
