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ANDY YE
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Name
Affiliation
Papers
ANDY YE
Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada
16
Collaborators
Citations
PageRank
27
98
9.20
Referers
Referees
References
251
332
177
Search Limit
100
332
Publications (16 rows)
Collaborators (27 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology
1
0.35
2020
A Scene-Based Augmented Reality Framework For Exhibits
0
0.34
2019
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures.
1
0.35
2018
A study on the accuracy of minimum width transistor area in estimating FPGA layout area.
1
0.35
2017
An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures
2
0.38
2016
An Empirical Analysis of the Fidelity of VPR Area Models
0
0.34
2016
Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection
0
0.34
2016
Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area
5
0.46
2015
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs
0
0.34
2012
Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications
1
0.37
2012
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
1
0.37
2012
The effect of multi-bit correlation on the design of field-programmable gate array routing resources
7
0.51
2011
Audio Scene Analysis Using Parametric Signal Features
3
0.40
2011
Hardware-Software Analysis Of Pole Model Features
0
0.34
2011
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling
70
3.41
2009
A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays
6
0.54
2008
1