Name
Affiliation
Papers
ANDY YE
Department of Electrical and Computer Engineering, Ryerson University, Toronto, ON, Canada
16
Collaborators
Citations 
PageRank 
27
98
9.20
Referers 
Referees 
References 
251
332
177
Search Limit
100332
Title
Citations
PageRank
Year
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology10.352020
A Scene-Based Augmented Reality Framework For Exhibits00.342019
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures.10.352018
A study on the accuracy of minimum width transistor area in estimating FPGA layout area.10.352017
An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures20.382016
An Empirical Analysis of the Fidelity of VPR Area Models00.342016
Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection00.342016
Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area50.462015
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs00.342012
Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications10.372012
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding10.372012
The effect of multi-bit correlation on the design of field-programmable gate array routing resources70.512011
Audio Scene Analysis Using Parametric Signal Features30.402011
Hardware-Software Analysis Of Pole Model Features00.342011
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling703.412009
A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays60.542008