| Pinning observability of competitive neural networks with different time-constants. | 1 | 0.35 | 2019 |
| Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators. | 1 | 0.36 | 2017 |
| Hardware implementation of machine vision systems: image and video processing. | 2 | 0.34 | 2013 |
| Improved gradient-based motion estimation on reconfigurable platforms | 0 | 0.34 | 2009 |
| Intellectual Property Protection Of Hdl Ip Cores Through Automated Signature Hosting | 0 | 0.34 | 2007 |
| Fast discrete Fourier transform computations using the reduced adder graph technique | 0 | 0.34 | 2007 |
| Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology | 3 | 0.45 | 2005 |
| Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks | 0 | 0.34 | 2005 |
| Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices | 0 | 0.34 | 2004 |
| Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic | 6 | 0.58 | 2003 |
| Design and Implementation of RNS-Based Adaptive Filters | 2 | 0.54 | 2003 |
| Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies | 12 | 0.81 | 2003 |
| Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic | 27 | 1.73 | 2001 |
| An interspike interval method for computing phase locking from neural firing. | 0 | 0.34 | 2000 |
| RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic | 9 | 0.91 | 1999 |
| Artificial implementation of auditory neurons: a comparison of biologically motivated models and a new transfer function oriented model. | 2 | 0.59 | 1997 |
| Convolutional Error Decoding with FPGAs | 1 | 0.51 | 1996 |
| Coherent Demodulation with FPGAs | 0 | 0.34 | 1996 |
| COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA | 7 | 1.00 | 1994 |
