| An optimized FPGA design of inverse quantization and transform for HEVC decoding blocks and validation in an SW/HW environment | 0 | 0.34 | 2020 |
| An Fpga Comparative Study Of High-Level And Low-Level Combined Designs For Hevc Intra, Inverse Quantization, And Idct/Idst 2d Modules | 0 | 0.34 | 2020 |
| Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks | 0 | 0.34 | 2019 |
| A Comparative Study Of Sorting Algorithms With Fpga Acceleration By High Level Synthesis | 0 | 0.34 | 2019 |
| ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures | 0 | 0.34 | 2019 |
| Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays | 4 | 0.38 | 2018 |
| An Embedded Multi-Sensor Data Fusion Design for Vehicle Perception Tasks. | 1 | 0.35 | 2018 |
| FPGA-Centric Design Process for Avionic Simulation and Test. | 2 | 0.41 | 2018 |
| New MIP model for multiprocessor scheduling problem with communication delays | 2 | 0.36 | 2017 |
| Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems. | 0 | 0.34 | 2017 |
| Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. | 5 | 0.52 | 2017 |
| Multi-level energy/power-aware design methodology for MPSoC. | 1 | 0.39 | 2017 |
| FPGA-Centric High Performance Embedded Computing: Challenges and Trends | 0 | 0.34 | 2017 |
| An Optimized Software Radio Application Using A Dynamic Slack Reclamation Technique On A Real Platform Omap 3530 | 0 | 0.34 | 2017 |
| Design Exploration Of Efficient Implementation On Soc Heterogeneous Platform: Hevc Intra Prediction Application | 1 | 0.36 | 2017 |
| A Comprehensive Approach for Camera/LIDAR Frame Alignment. | 0 | 0.34 | 2017 |
| An Efficient Hardware Implementation of TimSort and MergeSort Algorithms Using High Level Synthesis | 1 | 0.36 | 2017 |
| Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System | 0 | 0.34 | 2015 |
| A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only) | 1 | 0.43 | 2015 |
| Redefining the role of FPGAs in the next generation avionic systems (abstract only) | 1 | 0.36 | 2014 |
| Model-driven design flow for distributed control in reconfigurable FPGA systems | 0 | 0.34 | 2014 |
| Early power-aware Design Space Exploration for embedded systems: MPEG-2 case study. | 3 | 0.38 | 2014 |
| System-level power estimation tool for embedded processor based platforms | 14 | 0.79 | 2014 |
| Optimization of Matching and Scheduling on Heterogeneous CPU/FPGA Architectures. | 1 | 0.35 | 2013 |
| Heterogeneous CPU/FPGA Reconfigurable Computing System for Avionic Test Application | 0 | 0.34 | 2013 |
| An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC. | 12 | 0.66 | 2013 |
| A fast MPSoC virtual prototyping for intensive signal processing applications | 1 | 0.40 | 2012 |
| An efficient power estimation methodology for complex RISC processor-based platforms | 6 | 0.56 | 2012 |
| Abstract Clock-Based Design of a JPEG Encoder | 1 | 0.35 | 2012 |
| Dynamic reconfiguration of modular I/O IP cores for avionic applications | 8 | 0.69 | 2012 |
| A prototyping environment for high performance reconfigurable computing. | 1 | 0.37 | 2011 |
| Fast and accurate hybrid power estimation methodology for embedded systems. | 4 | 0.47 | 2011 |
| A Model-Driven Design Framework for Massively Parallel Embedded Systems | 45 | 1.92 | 2011 |
| Hybrid system level power consumption estimation for FPGA-based MPSoC | 12 | 0.68 | 2011 |
| A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design | 8 | 0.56 | 2011 |
| Dynamically reconfigurable architecture for a driver assistant system | 2 | 0.41 | 2011 |
| Toward generic and adaptive avionic test systems | 1 | 0.43 | 2011 |
| An efficient design methodology for hybrid avionic test systems | 1 | 0.38 | 2010 |
| An Improved Automotive Multiple Target Tracking System Design | 2 | 0.41 | 2010 |
| A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC | 1 | 0.38 | 2009 |
| An MPSoC Performance Estimation Framework Using Transaction Level Modeling | 13 | 0.74 | 2007 |
| Multilevel MPSOC simulation using an MDE approach. | 2 | 0.46 | 2007 |
| Estimating energy consumption for an MPSoC architectural exploration | 16 | 0.84 | 2006 |
