| VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations | 0 | 0.34 | 2021 |
| FPGA Checkpointing for Scientific Computing | 0 | 0.34 | 2021 |
| Scrooge Attack: Undervolting ARM Processors for Profit: Practical experience report | 0 | 0.34 | 2021 |
| A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures | 2 | 0.38 | 2020 |
| Checkpoint Restart Support for Heterogeneous HPC Applications | 1 | 0.36 | 2020 |
| Ground-Truth Prediction to Accelerate Soft-Error Impact Analysis for Iterative Methods | 0 | 0.34 | 2019 |
| Characterization of the Impact of Soft Errors on Iterative Methods. | 1 | 0.36 | 2018 |
| Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories. | 3 | 0.40 | 2018 |
| Fault Characterization Through FPGA Undervolting | 1 | 0.34 | 2018 |
| Comparative analysis of soft-error detection strategies: a case study with iterative methods | 2 | 0.49 | 2018 |
| Approximating a Multi-Grid Solver | 0 | 0.34 | 2018 |
| A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs | 1 | 0.34 | 2018 |
| Towards Ad Hoc Recovery for Soft Errors | 0 | 0.34 | 2018 |
| High Level Synthesis Based Hardware Accelerator Design for Processing SQL Queries | 1 | 0.35 | 2015 |
| Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators | 1 | 0.36 | 2014 |
| Power estimation tool for system on programmable chip based platforms (abstract only) | 0 | 0.34 | 2014 |
| Combining Error Detection and Transactional Memory for Energy-Efficient Computing below Safe Operation Margins | 1 | 0.36 | 2014 |
| System-level power estimation tool for embedded processor based platforms | 14 | 0.79 | 2014 |
| Improving the energy efficiency of hardware-assisted watchpoint systems | 0 | 0.34 | 2013 |
| Profile-guided transaction coalescing - lowering transactional overheads by merging transactions. | 3 | 0.38 | 2013 |
| Hardware transactional memory with software-defined conflicts | 2 | 0.36 | 2012 |
| TagTM - accelerating STMs with hardware tags for fast meta-data access | 1 | 0.35 | 2012 |
| Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing | 1 | 0.36 | 2011 |
| The Velox Transactional Memory Stack | 4 | 0.42 | 2010 |
| EazyHTM: EAger-LaZY hardware Transactional Memory | 62 | 1.59 | 2009 |
| The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment | 19 | 0.89 | 2008 |
| WormBench: a configurable workload for evaluating transactional memory systems | 11 | 0.58 | 2008 |
| Hardware transactional memory with operating system support, HTMOS | 0 | 0.34 | 2007 |
| Fuse: A Technique to Anticipate Failures due to Degradation in ALUs | 3 | 0.39 | 2007 |
| Exploiting Narrow Values for Soft Error Tolerance | 25 | 0.93 | 2006 |
| Combining compiler and runtime IPC predictions to reduce energy in next generation architectures | 5 | 0.50 | 2004 |
