Rajesh Chandrasekhara Panicker - Citegraph

Author Info

Name	Affiliation	Papers
RAJESH CHANDRASEKHARA PANICKER	Department of Electrical and Computer Engineering, National University of Singapore, Singapore	6
Collaborators	Citations	PageRank
8	38	3.76
Referers	Referees	References
144	82	28

Search Limit

100144

Publications (6 rows)

Collaborators (8 rows)

Referers (100 rows)

Referees (82 rows)

Title	Citations	PageRank	Year
Introducing FPGA-based Machine Learning on the Edge to Undergraduate Students.	0	0.34	2020
Adaptive Learning And Analytics In Engineering Education	0	0.34	2018
Development of an FPGA-based real-time P300 speller.	1	0.36	2012
An Asynchronous P300 BCI With SSVEP-Based Control State Detection.	33	1.89	2011
Asynchronous P300 BCI: SSVEP-based control state detection	0	0.34	2010
A Constrained Genetic Algorithm for Efficient Dimensionality Reduction for Pattern Classification	4	0.50	2007

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