Alejandro Valero - Citegraph

Author Info

Name	Affiliation	Papers
ALEJANDRO VALERO	Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain	20
Collaborators	Citations	PageRank
39	53	8.48
Referers	Referees	References
141	442	201

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100442

Publications (20 rows)

Collaborators (39 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A learning experience toward the understanding of abstraction-level interactions in parallel applications	0	0.34	2021
An Aging-Aware GPU Register File Design Based on Data Redundancy.	0	0.34	2019
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance	0	0.34	2019
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer	0	0.34	2019
Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache.	0	0.34	2018
Exploiting Data Compression to Mitigate Aging in GPU Register Files	0	0.34	2017
On Microarchitectural Mechanisms for Cache Wearout Reduction.	4	0.46	2017
Enhancing the L1 Data Cache Design to Mitigate HCI	2	0.37	2016
Design of Hybrid Second-Level Caches	5	0.42	2015
A reuse-based refresh policy for energy-aware eDRAM caches.	1	0.34	2015
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes	5	0.43	2013
Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches	2	0.36	2013
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity.	0	0.34	2013
Path Loss Modeling for Vehicular System Performance and Communication Protocols Evaluation	6	0.58	2013
Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches	0	0.34	2012
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches	5	0.49	2012
Combining recency of information with selective random and a victim cache in last-level caches	4	0.55	2012
Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour	0	0.34	2011
MRU-Tour-based Replacement Algorithms for Last-Level Caches	1	0.37	2011
An hybrid eDRAM/SRAM macrocell to implement first-level data caches	18	1.05	2009