| Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements | 39 | 2.95 | 2007 |
| A Framework for Architecture-Level Lifetime Reliability Modeling | 35 | 1.36 | 2007 |
| Temperature-limited microprocessors: Measurements and design implications | 0 | 0.34 | 2007 |
| CMP design space exploration subject to physical constraints | 83 | 4.26 | 2006 |
| Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices | 2 | 0.37 | 2005 |
| Performance, energy, and thermal considerations for SMT and CMP architectures | 74 | 5.67 | 2005 |
| Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors | 24 | 1.32 | 2005 |
| Implementing branch-predictor decay using quasi-static memory cells | 10 | 0.83 | 2004 |
| Understanding the Energy Efficiency of Simultaneous Multithreading | 25 | 2.06 | 2004 |
| Microarchitectural Techniques for Power Gating of Execution Units | 123 | 5.54 | 2004 |
| Spectral analysis for characterizing program power and performance | 7 | 0.74 | 2004 |
| Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization | 16 | 1.21 | 2004 |
| TCP: Tag Correlating Prefetchers | 30 | 1.41 | 2003 |
| Implementing Decay Techniques using 4T Quasi-Static Memory Cells | 4 | 0.47 | 2002 |
| Applying decay strategies to branch predictors for leakage energy savings | 28 | 1.59 | 2002 |
| Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. | 0 | 0.34 | 2002 |
| Let caches decay: reducing leakage energy via exploitation of cache generational behavior | 31 | 1.36 | 2002 |
| Managing leakage for transient data: decay and quasi-static 4T memory cells | 17 | 1.91 | 2002 |
| Cache decay: exploiting generational behavior to reduce cache leakage power | 408 | 33.40 | 2001 |
| Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads | 32 | 2.72 | 2001 |
| Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power | 16 | 1.64 | 2000 |
