| Adaptive and Scalable Predictive Page Policies for High Core-Count Server CPUs. | 0 | 0.34 | 2017 |
| Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration | 0 | 0.34 | 2010 |
| Complexity Effective Bypass Networks | 0 | 0.34 | 2009 |
| Exploring the Limits of Port Reduction in Centralized Register Files | 3 | 0.42 | 2009 |
| Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration | 0 | 0.34 | 2009 |
| Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration | 1 | 0.35 | 2009 |
| Cache Noise Prediction | 3 | 0.41 | 2008 |
| Scalable multi-cores with improved per-core performance using off-the-critical path reconfigurable hardware | 1 | 0.35 | 2008 |
| McGrid: framework for optimizing grid middleware on multi-core processors | 0 | 0.34 | 2007 |
| Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop | 0 | 0.34 | 2007 |
| Increasing cache capacity through word filtering | 2 | 0.39 | 2007 |
| Increasing the cache efficiency by eliminating noise | 13 | 0.97 | 2006 |
| Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors | 14 | 0.73 | 2006 |
| Address-Value Decoupling for Early Register Deallocation | 7 | 0.48 | 2006 |
| Self-checking instructions: reducing instruction redundancy for concurrent error detection | 6 | 0.53 | 2006 |
| Trade-offs in transient fault recovery schemes for redundant multithreaded processors | 6 | 0.43 | 2006 |
| Reducing latencies of pipelined cache accesses through set prediction | 3 | 0.42 | 2005 |
| Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency | 15 | 0.78 | 2005 |
| Restrictive Compression Techniques to Increase Level 1 Cache Capacity | 6 | 0.56 | 2005 |
| Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors | 1 | 0.35 | 2005 |
| The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems | 21 | 0.84 | 2004 |
| Bit-sliced datapath for energy-efficient high performance microprocessors | 6 | 0.47 | 2004 |
| Defining Wakeup Width for Efficient Dynamic Scheduling | 10 | 0.50 | 2004 |
| Single FU bypass networks for high clock rate superscalar processors | 1 | 0.35 | 2004 |
| Energy efficient asymmetrically ported register files | 24 | 0.93 | 2003 |
| Software caching vs. prefetching | 11 | 0.54 | 2002 |
| Hierarchical interconnects for on-chip clustering | 10 | 0.98 | 2002 |
| Related field analysis | 13 | 0.78 | 2001 |
| Evaluating the impact of memory system performance on software prefetching and locality optimizations | 25 | 2.02 | 2001 |
| Putting Data Value Predictors to Work in Fine-Grain Parallel Processors | 0 | 0.34 | 2001 |
