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STEPHEN V. KOSONOCKY
Author Info
Open Visualization
Name
Affiliation
Papers
STEPHEN V. KOSONOCKY
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
12
Collaborators
Citations
PageRank
47
177
18.28
Referers
Referees
References
461
283
85
Search Limit
100
461
Publications (12 rows)
Collaborators (47 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor.
0
0.34
2016
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS
5
1.48
2014
Are you having fun yet?
0
0.34
2010
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs
31
2.12
2007
Early Power-Aware Design & Validation: Myth Or Reality?
0
0.34
2007
Structured and tuned array generation (STAG) for high-performance random logic
0
0.34
2007
Multi-Dimensional Circuit and Micro-Architecture Level Optimization
3
0.70
2007
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
3
0.45
2005
Experimental measurement of a novel power gating structure with intermediate power saving mode
24
2.52
2004
Understanding and minimizing ground bounce during mode transition of power gating structures
94
7.49
2003
Low power integrated scan-retention mechanism
17
1.83
2002
Designing a testable system on a chip
0
0.34
1998
1