| MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. | 0 | 0.34 | 2021 |
| Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT | 0 | 0.34 | 2021 |
| 33.3 Via-Switch FPGA - 65nm CMOS Implementation and Architecture Extension for Al Applications. | 0 | 0.34 | 2020 |
| Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. | 0 | 0.34 | 2018 |
| Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. | 3 | 0.54 | 2018 |
| Area-Efficient Lut-Like Programmable Logic Using Atom Switch And Its Delay-Optimal Mapping Algorithm | 0 | 0.34 | 2017 |
| Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. | 0 | 0.34 | 2017 |
| Range Limiter Using Connection Bounding Box For Sa-Based Placement Of Mixed-Grained Reconfigurable Architecture | 0 | 0.34 | 2016 |
| A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch | 2 | 0.40 | 2016 |
| Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis | 0 | 0.34 | 2015 |
| A −0.5V-input voltage booster circuit for on-chip solar cells in 0.18µm CMOS technology | 0 | 0.34 | 2015 |
| An Error Correction Scheme Through Time Redundancy For Enhancing Persistent Soft-Error Tolerance Of Cgras | 0 | 0.34 | 2015 |
| Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design And Its Irradiation Testing | 3 | 0.54 | 2014 |
| Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits | 0 | 0.34 | 2014 |
| High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA | 1 | 0.35 | 2013 |
| Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis | 2 | 0.40 | 2013 |
| Parallel Acceleration Scheme For Monte Carlo Based Ssta Using Generalized Sta Processing Element | 0 | 0.34 | 2013 |
| Multi-trap RTN parameter extraction based on Bayesian inference | 3 | 0.46 | 2013 |
| Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability And C-Based Design | 0 | 0.34 | 2013 |
| A Cost-Effective Selective Tmr For Coarse-Grained Reconfigurable Architectures Based On Dfg-Level Vulnerability Analysis | 0 | 0.34 | 2013 |
| A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis | 3 | 0.41 | 2013 |
| Realization of frequency-domain circuit analysis through random walk | 0 | 0.34 | 2013 |
| Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array | 1 | 0.37 | 2013 |
| A Variability-Aware Energy-Minimization Strategy For Subthreshold Circuits | 1 | 0.37 | 2012 |
| Bayesian Estimation Of Multi-Trap Rtn Parameters Using Markov Chain Monte Carlo Method | 1 | 0.48 | 2012 |
| A high-throughput pipelined parallel architecture for JPEG XR encoding | 1 | 0.41 | 2012 |
| A fully pipelined implementation of Monte Carlo based SSTA on FPGAs | 1 | 0.36 | 2011 |
| Acceleration of random-walk-based linear circuit analysis using importance sampling | 3 | 0.41 | 2011 |
| A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization | 1 | 0.37 | 2011 |
| Reliability Evaluation Environment For Exploring Design Space Of Coarse-Grained Reconfigurable Architectures | 5 | 0.62 | 2010 |
| Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis | 11 | 0.75 | 2010 |
| Performance Evaluation and ASIC Design of LDPC Decoder for IEEE802.11n | 0 | 0.34 | 2010 |
| A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. | 0 | 0.34 | 2010 |
| Scan based process parameter estimation through path-delay inequalities | 0 | 0.34 | 2010 |
| Coarse-grained dynamically reconfigurable architecture with flexible reliability | 24 | 1.21 | 2009 |
| An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. | 0 | 0.34 | 2009 |
| A high-throughput pipelined architecture for JPEG XR encoding | 4 | 0.63 | 2009 |
| Efficient Memory Organization Framework For Jpeg2000 Entropy Codec | 0 | 0.34 | 2009 |
| Hardware Accelerator For Run-Time Learning Adopted In Object Recognition With Cascade Particle Filter | 1 | 0.39 | 2009 |
| Hot-Swapping architecture extension for mitigation of permanent functional unit faults | 6 | 0.59 | 2009 |
| Hardware Architecture for HOG Feature Extraction | 48 | 2.71 | 2009 |
| Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device | 1 | 0.41 | 2008 |
| Network Processor for High-Speed Network and Quick Programming | 0 | 0.34 | 2007 |
| Implementation of AV Streaming System Using Peer-to-Peer Communication | 3 | 10.26 | 2007 |
| A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture | 0 | 0.34 | 2007 |
| A Localization Scheme for Sensor Networks Based on Wireless Communication with Anchor Groups | 3 | 0.42 | 2006 |
| Pedestrian recognition in far-infrared images by combining boosting-based detection and skeleton-based stochastic tracking | 6 | 0.93 | 2006 |
| Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices | 1 | 0.37 | 2006 |
| Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback | 4 | 0.48 | 2006 |
| An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD | 0 | 0.34 | 2005 |
