Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver | 1 | 0.37 | 2014 |
Considering Crosstalk Effects in Statistical Timing Analysis | 0 | 0.34 | 2014 |
Transistor-level gate model based statistical timing analysis considering correlations | 2 | 0.35 | 2012 |
Crosstalk-aware statistical interconnect delay calculation | 2 | 0.38 | 2012 |
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs | 6 | 0.82 | 2011 |
Noise analysis of non-linear dynamic integrated circuits | 0 | 0.34 | 2010 |
RDE-based transistor-level gate simulation for statistical static timing analysis | 5 | 0.46 | 2010 |
Transistor-level gate modeling for nano CMOS circuit verification considering statistical process variations | 0 | 0.34 | 2010 |
Statistical Moment Estimation Of Delay And Power In Circuit Simulation | 1 | 0.38 | 2010 |
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning | 2 | 0.46 | 2004 |
Technical Program Committee | 0 | 0.34 | 2004 |
Polarized observability don't cares | 0 | 0.34 | 1996 |