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RICARDO POVOA
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Name
Affiliation
Papers
RICARDO POVOA
Univ Tecn Lisboa, Inst Super Tecn, Inst Telecomunicacoes, Lisbon, Portugal
26
Collaborators
Citations
PageRank
27
53
10.57
Referers
Referees
References
100
264
154
Search Limit
100
264
Publications (26 rows)
Collaborators (27 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing
1
0.37
2021
Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender
0
0.34
2020
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications
2
0.41
2020
A new family of CMOS inverter-based OTAs for biomedical and healthcare applications.
0
0.34
2020
FUZYE: A Fuzzy ${c}$ -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms
4
0.44
2020
Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications.
0
0.34
2020
Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop
4
0.54
2019
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement.
1
0.37
2018
Enhanced Analog And Rf Ic Sizing Methodology Using Pca And Nsga-Ii Optimization Kernel
0
0.34
2018
Second-order compensation BGR with low TC and high performance for space applications.
0
0.34
2018
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
1
0.37
2018
An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations
0
0.34
2018
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving.
1
0.37
2018
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization
1
0.36
2017
Systematic design of a voltage controlled oscillator using a layout-aware approach
1
0.36
2017
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks
0
0.34
2017
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing.
0
0.34
2017
Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations
1
0.37
2016
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques.
10
0.67
2016
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation.
10
0.67
2016
Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer.
0
0.34
2016
Current-flow and current-density-aware multi-objective optimization of analog IC placement.
3
0.49
2016
Floorplan-aware analog IC sizing and optimization based on topological constraints.
10
0.64
2015
A voltage-combiners-biased amplifier with enhanced gain and speed using current starving
1
0.37
2015
A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner
1
0.37
2014
A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis.
1
0.35
2013
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