| A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. | 0 | 0.34 | 2018 |
| Rethinking Numerical Representations for Deep Neural Networks. | 0 | 0.34 | 2018 |
| A 1.25pJ/bit 0.048mm<sup>2</sup> AES core with DPA resistance for IoT devices | 2 | 0.42 | 2017 |
| 20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. | 0 | 0.34 | 2017 |
| Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. | 0 | 0.34 | 2016 |
| A 5.5GHz 0.84TOPS/mm<sup>2</sup> neural network engine with stream architecture and resonant clock mesh | 0 | 0.34 | 2016 |
| 1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks | 11 | 0.73 | 2015 |
| A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors | 0 | 0.34 | 2015 |
| Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling | 1 | 0.35 | 2015 |
| Computational sprinting on a hardware/software testbed | 24 | 1.03 | 2013 |
| Utilizing Dark Silicon to Save Energy with Computational Sprinting | 10 | 0.53 | 2013 |
| Designing for Responsiveness with Computational Sprinting | 4 | 0.36 | 2013 |
| Computational sprinting | 34 | 1.39 | 2012 |
| Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic | 5 | 0.46 | 2012 |
| A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. | 3 | 0.60 | 2011 |
| 187 MHz Subthreshold-Supply Charge-Recovery FIR | 16 | 1.33 | 2010 |
| Resonant-Clock Latch-Based Design | 21 | 1.37 | 2008 |
| A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs | 31 | 2.12 | 2007 |
| A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. | 1 | 0.53 | 2007 |
| Energy-Efficient GHz-Class Charge-Recovery Logic | 22 | 1.82 | 2007 |
| Skew spreading for peak current reduction | 3 | 0.47 | 2007 |
| Parallelizing post-placement timing optimization | 1 | 0.36 | 2006 |
| Charge-Recovery Computing on Silicon | 24 | 1.60 | 2005 |
| Two-Phase Resonant Clock Distribution | 5 | 0.52 | 2005 |
| Boost Logic: A High Speed Energy Recovery Circuit Family | 4 | 0.59 | 2005 |
| RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power | 1 | 0.36 | 2005 |
| A GHz-class charge recovery logic | 0 | 0.34 | 2005 |
| Multi-Session Partitioning for Parallel Timing Optimization | 0 | 0.34 | 2005 |
| Fast, efficient, recovering, and irreversible | 0 | 0.34 | 2005 |
| Empirical evaluation of timing and power in resonant clock distribution | 3 | 0.49 | 2004 |
| An algorithm for geometric load balancing with two constraints | 0 | 0.34 | 2004 |
| Constant-load energy recovery memory for efficient high-speed operation | 2 | 0.46 | 2004 |
| Experimental evaluation of resonant clock distribution | 2 | 0.43 | 2004 |
| Energy Recovering ASIC Design | 7 | 1.04 | 2003 |
| Block-based multiperiod dynamic memory design for low data-retention power | 22 | 3.64 | 2003 |
| Design of a 20-Mb/s 256-state viterbi decoder | 7 | 0.50 | 2003 |
| A true single-phase energy-recovery multiplier | 9 | 0.74 | 2003 |
| HyPE: hybrid power estimation for IP-based programmable systems | 2 | 0.38 | 2003 |
| A 225 MHz resonant clocked ASIC chip | 11 | 1.45 | 2003 |
| Reduced delay uncertainty in high performance clock distribution networks | 17 | 1.31 | 2003 |
| Design of a high-throughput low-power IS95 Viterbi decoder | 3 | 0.54 | 2002 |
| Energy recovering static memory | 4 | 0.57 | 2002 |
| Incorporation of input glitches into power macromodeling | 8 | 0.62 | 2002 |
| A true single-phase 8-bit adiabatic multiplier | 14 | 1.58 | 2001 |
| A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty | 10 | 0.69 | 2001 |
| A static power estimation methodolodgy for IP-based design | 9 | 0.61 | 2001 |
| True single-phase adiabatic circuitry | 21 | 2.01 | 2001 |
| A resonant clock generator for single-phase adiabatic systems | 12 | 1.37 | 2001 |
| Design, verification, and test of a true single-phase 8-bit adiabatic multiplier | 6 | 0.94 | 2001 |
| Optimizing computations for effective block-processing | 7 | 0.60 | 2000 |
