GStreamMiner: A GPU-accelerated Data Stream Mining Framework | 0 | 0.34 | 2016 |
Matrix-Based XML Stream Processing Using a GPU | 0 | 0.34 | 2015 |
Online Multi-Dimensional Regression Analysis On Concept-Drifting Data Streams | 0 | 0.34 | 2014 |
Context Generator and Behavior Translator in a Multilayer Architecture for a Modular Development Process of Cyber-Physical Robot Systems | 6 | 0.44 | 2014 |
Gpu Accelerated Item-Based Collaborative Filtering For Big-Data Applications | 9 | 0.56 | 2013 |
Hyper-structure mining of frequent patterns in uncertain data streams. | 2 | 0.37 | 2013 |
Particle Swarm Optimization on a GPU. | 6 | 0.44 | 2012 |
Instant Multiunit Resource Hardware Deadlock Detection Scheme for System-on-Chips | 0 | 0.34 | 2012 |
Multi-biomarker panel selection on a GPU | 0 | 0.34 | 2012 |
A parallel multi-unit resource deadlock detection algorithm with O(log2(min(m,n))) overall run-time complexity | 3 | 0.50 | 2011 |
StreamFitter: a real time linear regression analysis system for continuous data streams | 6 | 0.47 | 2011 |
A Novel Multicontext Coarse-Grained Reconfigurable Architecture (CGRA) For Accelerating Column-Oriented Databases | 0 | 0.34 | 2011 |
A True O(1) Parallel Deadlock Detection Algorithm for Single-Unit Resource Systems and Its Hardware Implementation | 7 | 0.53 | 2010 |
Symbiote: a reconfigurable logic assisted data streammanagement system (RLADSMS) | 0 | 0.34 | 2010 |
An O(n) Parallel Shortest Path Algorithm and Its Hardware Implementation | 0 | 0.34 | 2010 |
A General Purpose FPGA Data Filter for Data Stream Processing | 0 | 0.34 | 2010 |
Multiprocessor simulation using communicating sequential processes | 1 | 0.36 | 2010 |
An O(L) Parallel Shortest Path Algorithm | 1 | 0.36 | 2009 |
An XML-Based ADL Framework for Automatic Generation of Multithreaded Computer Architecture Simulators | 0 | 0.34 | 2009 |
A Novel Multicontext Coarse-Grained Join Accelerator for Column-Oriented Databases | 1 | 0.37 | 2009 |
A Novel O(1) Deadlock Detection Methodology for Multiunit Resource Systems and Its Hardware Implementation for System-on-Chip | 5 | 0.47 | 2008 |
A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time Complexity | 0 | 0.34 | 2008 |
Characterization of TPC-H queries for a column-oriented database on a dual-core amd athlon processor | 1 | 0.35 | 2008 |
Main Memory DBMS on Modern Processors, a Scalable Approach for Database Performance Characterization Using Simulation | 0 | 0.34 | 2008 |
R-tree: A Hardware Implementation | 4 | 0.48 | 2008 |
A Novel O(1) Parallel Deadlock Detection Algorithm And Architecture For Multi-Unit Resource Systems | 1 | 0.38 | 2007 |
A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip | 3 | 0.54 | 2007 |
Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors | 3 | 0.40 | 2007 |
Simulation Of Hybrid Computer Architectures: Simulators, Methodologies And Recommendations | 2 | 0.42 | 2007 |
An o(min(m, n)) parallel deadlock detection algorithm | 4 | 0.68 | 2005 |
A novel O(n) parallel banker's algorithm for System-on-a-Chip | 2 | 0.46 | 2005 |
A novel deadlock avoidance algorithm and its hardware implementation | 2 | 0.42 | 2004 |
A comparison of the RTU hardware RTOS with a hardware/software RTOS | 26 | 2.20 | 2003 |
A system-on-a-chip lock cache with task preemption support | 9 | 1.70 | 2001 |